LTC3025IDC#TRMPBF

LTC3025
7
3025fd
using the formula in Figure 2. Note that in shutdown the
output is turned off and the divider current will be zero
once C
OUT
is discharged.
The LTC3025 operates at a relatively high gain of –0.7µV/
mA referred to the ADJ input. Thus a load current change
of 1mA to 300mA produces a –0.2mV drop at the ADJ
input. To calculate the change referred to the output sim-
ply multiply by the gain of the feedback network (i. e. ,1
+ R2/R1). For example, to program the output for 1.2V
choose R2/R1 = 2. In this example, an output current
change of 1mA to 300mA produces –0.2mV • (1 + 2) =
0.6mV drop at the output.
Because the ADJ pin is relatively high impedance (depend-
ing on the resistor divider used) , stray capacitance at this
pin should be minimized (<10pF) to prevent phase shift
in the error amplifi er loop. Additionally, special attention
should be given to any stray capacitances that can couple
external signals onto the ADJ pin producing undesirable
output ripple. For optimum performance connect the ADJ
pin to R1 and R2 with a short PCB trace and minimize all
other stray capacitance to the ADJ pin.
()
OUT
R1
R2
3025 F02
C
OUT
R2
R1
V
OUT
= 0.4V 1
ADJ
GND
Figure 2. Programming the LTC3025
APPLICATIONS INFORMATION
Output Capacitance and Transient Response
The LTC3025 is designed to be stable with a wide range of
ceramic output capacitors. The ESR of the output capaci-
tor affects stability, most notably with small capacitors. A
minimum output capacitor of 1µF with an ESR of 0.05Ω
or less is recommended to ensure stability. The LTC3025
is a micropower device and output transient response
will be a function of output capacitance. Larger values
of output capacitance decrease the peak deviations and
provide improved transient response for larger load current
changes. Note that bypass capacitors used to decouple
individual components powered by the LTC3025 will
increase the effective output capacitor value. High ESR
tantalum and electrolytic capacitors may be used, but
a low ESR ceramic capacitor must be in parallel at the
output. There is no minimum ESR or maximum capacitor
size requirements.
Extra consideration must be given to the use of ceramic
capacitors. Ceramic capacitors are manufactured with a
variety of dielectrics, each with different behavior across
temperature and applied voltage. The most common di-
electrics used are Z5U, Y5V, X5R and X7R. The Z5U and
Y5V dielectrics are good for providing high capacitances
in a small package, but exhibit large voltage and tem-
perature coeffi cients as shown in Figures 3 and 4. When
used with a 2V regulator, a 1µF Y5V capacitor can lose as
much as 75% of its initial capacitance over the operating
DC BIAS VOLTAGE (V)
CHANGE IN VALUE (%)
3025 F03
20
0
–20
–40
–60
–80
–100
0
4
8
10
26
X5R
Y5V
BOTH CAPACITORS ARE 1µF,
10V, 0603 CASE SIZE
Figure 3. Ceramic Capacitor DC Bias Characteristics
TEMPERATURE (°C)
–50
–100
CHANGE IN VALUE (%)
–80
–60
–40
–20
X5R
Y5V
20
–25
02550
3025 F04
75
0
BOTH CAPACITORS ARE 1µF,
10V, 0603 CASE SIZE
Figure 4. Ceramic Capacitor Temperature Characteristics
LTC3025
8
3025fd
temperature range. The X5R and X7R dielectrics result in
more stable characteristics and are usually more suitable
for use as the output capacitor. The X7R type has better
stability across temperature, while the X5R is less expensive
and is available in higher values. In all cases, the output
capacitance should never drop below 0.4µF, or instability
or degraded performance may occur.
Thermal Considerations
The power handling capability of the device will be limited
by the maximum rated junction temperature (125°C). The
power dissipated by the device will be the output current
multiplied by the input/output voltage differential:
(I
OUT
) (V
IN
– V
OUT
)
Note that the BIAS current is less than 300µA even under
heavy loads, so its power consumption can be ignored
for thermal calculations.
The LTC3025 has internal thermal limiting designed to
protect the device during momentary overload conditions.
For continuous normal conditions, the maximum junction
temperature rating of 125°C must not be exceeded. It is
important to give careful consideration to all sources of
thermal resistance from junction to ambient. Additional
heat sources mounted nearby must also be considered.
For surface mount devices, heat sinking is accomplished
by using the heat-spreading capabilities of the PC board
and its copper traces. Copper board stiffeners and plated
through holes can also be used to spread the heat gener-
ated by power devices.
The LTC3025 2mm × 2mm DFN package is specifi ed as hav-
ing a junction-to-ambient thermal resistance of 102°C/W,
which assumes a minimal heat spreading copper plane. The
actual thermal resistance can be reduced substantially by
connecting the package directly to a good heat spreading
ground plane. When soldered to 2500mm
2
double-sided
1 oz. copper plane, the actual junction-to-ambient thermal
resistance can be less than 60°C/W.
Calculating Junction Temperature
Example: Given an output voltage of 1.2V, an input voltage
of 1.8V to 3V, an output current range of 0mA to 100mA
and a maximum ambient temperature of 50°C, what will
the maximum junction temperature be?
The power dissipated by the device will be equal to:
I
OUT(MAX)
(V
IN(MAX)
– V
OUT
)
where:
I
OUT(MAX)
= 100mA
V
IN(MAX)
= 3V
So:
P = 100mA(3V – 1.2V) = 0.18W
Even under worst-case conditions, the LTC3025’s BIAS pin
power dissipation is only about 1mW, thus can be ignored.
Assuming a junction-to-ambient thermal resistance of
102°C/W, the junction temperature rise above ambient
will be approximately equal to:
0.18W(102°C/W) = 18.4°C
The maximum junction temperature will then be equal to
the maximum junction temperature rise above ambient
plus the maximum ambient temperature or:
T = 50°C + 18.4°C = 68.4°C
Short-Circuit/Thermal Protection
The LTC3025 has built-in short-circuit current limiting as
well as overtemperature protection. During short-circuit
conditions, internal circuitry automatically limits the output
current to approximately 600mA. At higher temperatures, or
in cases where internal power dissipation causes excessive
self heating on chip, the thermal shutdown circuitry will
shut down the LDO when the junction temperature exceeds
approximately 150°C. It will re enable the LDO once the
junction temperature drops back to approximately 140°C.
APPLICATIONS INFORMATION
LTC3025
9
3025fd
APPLICATIONS INFORMATION
The LTC3025 will cycle in and out of thermal shutdown
without latch-up or damage until the overstress condition
is removed. Long term overstress (T
J
> 125°C) should be
avoided as it can degrade the performance or shorten the
life of the part.
Soft-Start Operation
The LTC3025 includes a soft-start feature to prevent
excessive current fl ow during start-up. When the LDO is
enabled, the soft-start circuitry gradually increases the LDO
reference voltage from 0V to 0.4V over a period of about
600µs. There is a short 700µs delay from the time the
part is enabled until the LDO output starts to rise. Figure 5
shows the start-up and shutdown output waveform.
V
OUT
Start-Up and Supply Sequencing
During power-up, the output shutdown circuitry is not
active below V
IN
of about 0.65V DC (typical). As a result,
the output voltage can drift up during power-up due to
leakage current (<1 mA typical) from V
IN
to V
OUT
. At 0.9V
input, the shutdown circuitry is active and the output is
actively held off. This usually causes no circuit problems
and is similar to 3-terminal regulators such as the LT3080,
LT1086 and LT317 which have no ground pin and can have
the output rise under some conditions. A slowly rising
V
IN
with the part enabled may result in non-monotonic
ramping of V
OUT
due to LDO circuitry becoming active at
V
IN
of about 0.65V (typical) as well.
With fast rising inputs (>1V/ms) or with suffi cient resis-
tive load on V
OUT
, output voltage rise during power-up is
reduced or eliminated. Such conditions also reduce or
eliminate non-monotonic initial power-up with the part
enabled. If V
BIAS
is sequenced up before V
IN
, the leakage
current from V
IN
to V
OUT
may increase until the shutdown
circuitry is active at a V
IN
of about 0.65V typical. Thus,
to minimize V
OUT
rise during start-up, sequence up V
IN
before V
BIAS
. At V
IN
= 0.9V, the output is actively held off
in shutdown or it is actively held on when enabled under
all conditions.
OFF
1.2V
0V
ON
SHDN
V
OUT
200mV/DIV
T
A
= 25°C
V
IN
= 1.5V
V
BIAS
= 3.6V
C
OUT
= 1µF
R
LOAD
= 4
500µs/DIV
3025 F05
Figure 5. Output Start-Up and Shutdown

LTC3025IDC#TRMPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
LDO Voltage Regulators 300mA Micropower VLDO Linear Regulator
Lifecycle:
New from this manufacturer.
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