PCA85162 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 9 April 2015 34 of 56
NXP Semiconductors
PCA85162
32 x 4 automotive LCD driver for low multiplex rates
12. Static characteristics
Table 19. Static characteristics
V
DD
= 1.8 V to 5.5 V; V
SS
= 0 V; V
LCD
= 2.5 V to 8.0 V; T
amb
=
40
C to +95
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Supplies
V
DD
supply voltage 1.8 - 5.5 V
V
LCD
LCD supply voltage
[1]
2.5- 8.0V
I
DD
supply current f
clk(ext)
= 1536 Hz
[2][3]
-3.57A
V
DD
=3.0V; T
amb
=25C-2.7-A
I
DD(LCD)
LCD supply current f
clk(ext)
= 1536 Hz
[2]
-2332A
V
LCD
=3.0V; T
amb
=25C-13-A
Logic
[4]
V
P(POR)
power-on reset supply
voltage
1.01.31.6V
V
IL
LOW-level input
voltage
on pins CLK, SYNC, OSC, A0 to
A2, SA0, SCL, SDA
V
SS
-0.3V
DD
V
V
IH
HIGH-level input
voltage
on pins CLK, SYNC, OSC, A0 to
A2, SA0, SCL, SDA
[5][6]
0.7V
DD
-V
DD
V
I
OL
LOW-level output
current
output sink current;
V
OL
=0.4V; V
DD
=5V
on pins CLK and SYNC
1- - mA
on pin SDA 3 - - mA
I
OH(CLK)
HIGH-level output
current on pin CLK
output source current;
V
OH
=4.6V; V
DD
=5V
1- - mA
I
L
leakage current V
I
=V
DD
or V
SS
;
on pins CLK, SCL, SDA, A0 to
A2, and SA0
1- +1A
I
L(OSC)
leakage current on pin
OSC
V
I
=V
DD
1- +1A
C
I
input capacitance
[7]
--7pF
PCA85162 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 9 April 2015 35 of 56
NXP Semiconductors
PCA85162
32 x 4 automotive LCD driver for low multiplex rates
[1] V
LCD
> 3 V for
1
3
bias.
[2] LCD outputs are open-circuit; inputs at V
SS
or V
DD
; external clock with 50 % duty factor; I
2
C-bus inactive.
[3] For typical values, see Figure 23
.
[4] The I
2
C-bus interface of PCA85162 is 5 V tolerant.
[5] When tested, I
2
C pins SCL and SDA have no diode to V
DD
and may be driven to the V
I
limiting values given in Table 18 (see Figure 22
as well).
[6] Propagation delay of driver between clock (CLK) and LCD driving signals.
[7] Periodically sampled, not 100 % tested.
[8] Outputs measured one at a time.
LCD outputs
V
O
output voltage
variation
on pins BP0 to BP3 and
S0 to S31
100 - +100 mV
R
O
output resistance V
LCD
= 5 V
[8]
on pins BP0 to BP3 - 1.5 - k
on pins S0 to S31 - 6.0 - k
Table 19. Static characteristics …continued
V
DD
= 1.8 V to 5.5 V; V
SS
= 0 V; V
LCD
= 2.5 V to 8.0 V; T
amb
=
40
C to +95
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
T
amb
=30C; 1:4 multiplex drive mode; V
LCD
= 6.5 V; f
clk(ext)
= 1.536 kHz; all RAM written with
logic 1; no display connected; I
2
C-bus inactive.
Fig 23. Typical I
DD
with respect to V
DD
DDD
9
''
9
,
''''
,
''
$$$
PCA85162 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 9 April 2015 36 of 56
NXP Semiconductors
PCA85162
32 x 4 automotive LCD driver for low multiplex rates
13. Dynamic characteristics
Table 20. Dynamic characteristics
V
DD
= 1.8 V to 5.5 V; V
SS
= 0 V; V
LCD
= 2.5 V to 8.0 V; T
amb
=
40
C to +95
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Clock
f
clk(int)
internal clock
frequency
[1]
1920 2640 3600 Hz
f
clk(ext)
external clock
frequency
960 - 4800 Hz
f
fr
frame frequency internal clock 80 110 150 Hz
external clock 40 - 200 Hz
t
clk(H)
HIGH-level clock time 60 - - s
t
clk(L)
LOW-level clock time 60 - - s
Synchronization
t
PD(SYNC_N)
SYNC propagation
delay
-30-ns
t
SYNC_NL
SYNC LOW time 1 - - s
t
PD(drv)
driver propagation
delay
V
LCD
= 5 V
[2]
--30s
I
2
C-bus
[3]
Pin SCL
f
SCL
SCL clock frequency - - 400 kHz
t
LOW
LOW period of the
SCL clock
1.3 - - s
t
HIGH
HIGH period of the
SCL clock
0.6 - - s
Pin SDA
t
SU;DAT
data set-up time 100 - - ns
t
HD;DAT
data hold time 0 - - ns
Pins SCL and SDA
t
BUF
bus free time between
a STOP and START
condition
1.3 - - s
t
SU;STO
set-up time for STOP
condition
0.6 - - s
t
HD;STA
hold time (repeated)
START condition
0.6 - - s
t
SU;STA
set-up time for a
repeated START
condition
0.6 - - s
t
r
rise time of both SDA
and SCL signals
f
SCL
= 400 kHz - - 0.3 s
f
SCL
< 125 kHz - - 1.0 s

PCA85162T/Q900/1,1

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
LCD Drivers 32 SGMT 4800Hz
Lifecycle:
New from this manufacturer.
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