Table 13: DDR2 I
DD
Specifications and Conditions (Die Revision A) – 1GB
Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) com-
ponent data sheet
Parameter Symbol
-80E/
-800 -667 -53E -40E Units
Operating one bank active-precharge current:
t
CK =
t
CK (I
DD
),
t
RC =
t
RC (I
DD
),
t
RAS =
t
RAS MIN (I
DD
); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data bus inputs are switching
I
DD0
900 810 720 630 mA
Operating one bank active-read-precharge current: I
OUT
= 0mA; BL =
4, CL = CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RC =
t
RC (I
DD
),
t
RAS =
t
RAS MIN
(I
DD
),
t
RCD =
t
RCD (I
DD
); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data pattern is same as I
DD4W
I
DD1
990 900 855 720 mA
Precharge power-down current: All device banks idle;
t
CK =
t
CK (I
DD
);
CKE is LOW; Other control and address bus inputs are stable; Data bus in-
puts are floating
I
DD2P
63 63 63 63 mA
Precharge quiet standby current: All device banks idle;
t
CK =
t
CK (I
DD
);
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
Data bus inputs are floating
I
DD2Q
585 495 369 315 mA
Precharge standby current: All device banks idle;
t
CK =
t
CK (I
DD
); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are switching; Da-
ta bus inputs are switching
I
DD2N
630 540 405 360 mA
Active power-down current: All device banks open;
t
CK
=
t
CK (I
DD
); CKE is LOW; Other control and address bus in-
puts are stable; Data bus inputs are floating
Fast PDN exit
MR[12] = 0
I
DD3P
405 360 315 315 mA
Slow PDN exit
MR[12] = 1
126 126 126 126
Active standby current: All device banks open;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS MAX (I
DD
),
t
RP =
t
RP (I
DD
); CKE is HIGH, S# is HIGH between valid com-
mands; Other control and address bus inputs are switching; Data bus
inputs are switching
I
DD3N
675 630 495 405 mA
Operating burst write current: All device banks open; Continuous
burst writes; BL = 4, CL = CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS MAX
(I
DD
),
t
RP =
t
RP (I
DD
); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are switching
I
DD4W
1665 1440 1170 990 mA
Operating burst read current: All device banks open; Continuous burst
read, I
OUT
= 0mA; BL = 4, CL = CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS
MAX (I
DD
),
t
RP =
t
RP (I
DD
); CKE is HIGH, S# is HIGH between valid com-
mands; Address bus inputs are switching; Data bus inputs are switching
I
DD4R
1710 1440 1305 990 mA
Burst refresh current:
t
CK =
t
CK (I
DD
); REFRESH command at every
t
RFC
(I
DD
) interval; CKE is HIGH, S# is HIGH between valid commands; Other con-
trol and address bus inputs are switching; Data bus inputs are switching
I
DD5
2520 2700 2250 1980 mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
I
DD6
63 63 63 63 mA
256MB, 512MB, 1GB (x72, SR, ECC) 240-Pin DDR2 UDIMM
I
DD
Specifications
PDF: 09005aef80e8ad4d
htf9c32_64_128x72ay – Rev. F 3/10 EN
16
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