74HCT157DR2G

74HCT157
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4
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input t
r
= t
f
= 6.0 ns)
Symbol Parameter
V
CC
(V)
Guaranteed Limit
Unit
– 55 to
25_C
v 85_C v 125_C
t
PLH
,
t
PHL
Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 4)
4.5 21 26 32 ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Select to Output Y
(Figures 2 and 4)
4.5 22 28 33 ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Output Enable to Output Y
(Figures 3 and 4)
4.5 20 25 30 ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
4.5 15 19 22 ns
C
in
Maximum Input Capacitance 10 10 10 pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor HighSpeed CMOS Data Book (DL129/D).
C
PD
Power Dissipation Capacitance (Per Package)*
Typical @ 25°C, V
CC
= 5.0 V
pF
33
* Used to determine the noload dynamic power consumption: P
D
= C
PD
V
CC
2
f + I
CC
V
CC
. For load considerations, see Chapter 2 of the
ON Semiconductor HighSpeed CMOS Data Book (DL129/D).
74HCT157
http://onsemi.com
5
PIN DESCRIPTIONS
INPUTS
A0, A1, A2, A3 (Pins 2, 5, 11, 14)
Nibble A inputs. The data present on these pins is
transferred to the outputs when the Select input is at a low
level and the Output Enable input is at a low level. The data
is presented to the outputs in noninverted form.
B0, B1, B2, B3 (Pins 3, 6, 10, 13)
Nibble B inputs. The data present on these pins is
transferred to the outputs when the Select input is at a high
level and the Output Enable input is at a low level. The data
is presented to the outputs in noninverted form.
OUTPUTS
Y0, Y1, Y2, Y3 (Pins 4, 7, 9, 12)
Data outputs. The selected input Nibble is presented at
these outputs when the Output Enable input is at a low level.
The data present on these pins is in its noninverted form. For
the Output Enable input at a high level, the outputs are at a
low level.
CONTROL INPUTS
Select (Pin 1)
Nibble select. This input determines the data word to be
transferred to the outputs. A low level on this input selects
the A inputs and a high level selects the B inputs.
Output Enable (Pin 15)
Output Enable input. A low level on this input allows the
selected input data to be presented at the outputs. A high
level on this input sets all outputs to a low level.
SWITCHING WAVEFORMS
INPUT A OR B
OUTPUT
ENABLE
t
PLH
t
PHL
t
r
t
f
V
CC
GND
t
THL
t
TLH
10%
50%
90%
10%
50%
90%
OUTPUT Y
*Includes all probe and jig capacitance
C
L
*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
t
r
t
f
V
CC
GND
OUTPUT Y
t
PHL
t
PLH
10%
50%
90%
10%
50%
90%
t
TLH
t
THL
t
r
t
f
V
CC
GND
SELECT
OUTPUT Y
t
PHL
t
PLH
t
TLH
t
THL
10%
50%
90%
10%
50%
90%
Figure 3. HCT157 Figure 4. Y versus Selected, Noninverted
Figure 5. HCT157
Figure 6. Test Circuit
74HCT157
http://onsemi.com
6
EXPANDED LOGIC DIAGRAM
4
7
9
12
2
3
5
6
11
10
14
13
15
1
A0
B0
A1
B1
A2
B2
A3
B3
Y0
Y1
Y2
Y3
OUTPUT ENABLE
SELECT
DATA
OUTPUTS
NIBBLE
OUTPUTS

74HCT157DR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
IC SELECTOR/MUX QUAD 2CH 16-SOIC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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