CY28410-2
Document #: 38-07747 Rev *.* Page 5 of 17
Byte 1: Control Register 1
Bit @Pup Name Description
7 1 PCIF0 PCIF0 Output Enable
0 = Disabled, 1 = Enabled
6 1 DOT_96T/C DOT_96 MHz Output Enable
0 = Disable (Hi-Z), 1 = Enabled
5 1 USB_48 USB_48 MHz Output Enable
0 = Disabled, 1 = Enabled
4 1 REF REF Output Enable
0 = Disabled, 1 = Enabled
3 0 CPU PLL Spread
Percentage
Select CPU PLL Spread Percentage
0: –0.5% Downspread
1:±0.25% Centerspread
2 1 CPU[T/C]1 CPU[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enabled
1 1 CPU[T/C]0 CPU[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enabled
0 0 CPUT/C
SRCT/C
PCIF
PCI
Spread Spectrum Enable
0 = Spread off, 1 = Spread on
Byte 2: Control Register 2
Bit @Pup Name Description
7 1 PCI5 PCI5 Output Enable
0 = Disabled, 1 = Enabled
6 1 PCI4 PCI4 Output Enable
0 = Disabled, 1 = Enabled
5 1 PCI3 PCI3 Output Enable
0 = Disabled, 1 = Enabled
4 1 PCI2 PCI2 Output Enable
0 = Disabled, 1 = Enabled
3 1 PCI1 PCI1 Output Enable
0 = Disabled, 1 = Enabled
2 1 PCI0 PCI0 Output Enable
0 = Disabled, 1 = Enabled
1 1 PCIF2 PCIF2 Output Enable
0 = Disabled, 1 = Enabled
0 1 PCIF1 PCIF1 Output Enable
0 = Disabled, 1 = Enabled
Byte 3: Control Register 3
Bit @Pup Name Description
7 0 SRC7 Allow control of SRC[T/C]7 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
6 0 SRC6 Allow control of SRC[T/C]6 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
5 0 SRC5 Allow control of SRC[T/C]5 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
4 0 SRC4 Allow control of SRC[T/C]4 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
3 0 SRC3 Allow control of SRC[T/C]3 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#