AD5100YRQZ-1RL7 Datasheet AD5100YRQZ-1RL7, AD5100YRQZ-0 | P28-P30

AD5100

Rev. A | Page 27 of 36

WRITING DATA TO AD5100

When writing data to the AD5100, the user begins by writing

an address byte followed by the R/

bit set to 0. The AD5100

acknowledges (if the correct address byte is used) by pulling

the SDA line low during the ninth clock pulse. The user then

follows with two data bytes. The first data byte is the address of

the internal data register to be written to, which is stored in the

address pointer register. The second byte is the data to be written

to the internal data register. After each byte, the AD5100

acknowledges by pulling the SDA line low during the ninth

clock pulse. illustrates this operation. Figure 21

READING DATA FROM AD5100

When reading data from an AD5100 register, there are two

possibilities.

• If the AD5100 address pointer register value is unknown

or not at the desired value, it is first necessary to set it to

the correct value before data can be read from the desired

data register. This is done by performing a write to the

AD5100, but only a value containing the register address

is sent because data is not to be written to the register. This

is shown in Figure 22. A read operation is then performed

consisting of the serial bus address, R/

bit set to 1,

followed by the data byte from the data register. This is

shown in . Figure 23

• If the address pointer is known to be already at the desired

address, data can be read from the corresponding data

Table 14 shows the readback data byte structure. Bits[6:0] con-

tain the data from the register just read. Bit 7 is a reserved bit

and should be ignored for normal read operations. The majority

of AD5100 registers are four bits wide, with only the fault detect

and status register and disable special functions register at seven

bits and five bits wide, respectively.

Table 14. Readback Data Byte Structure

Bit Number Function

7 Reserved

6 D6

5 D5

4 D4

3 D3

2 D2

1 D1

0 D0 (LSB)

5692-022

SDA

FRAME 1

SLAVE ADDRESS BYTE

FRAME 2

ADDRESS POINTER BYTE

FRAME 3

DATA BYTE

SCL

ACK. BY

AD5100

ACK. BY

AD5100

ACK. BY

AD5100

STOP BY

MASTER

START BY

MASTER

AD0

R/W

OTP

AP6

AP5 AP4

AP3

AP2

AP1

AP0

D6 D5 D4 D3 D2 D1

Figure 21. Writing a Register Address to the Address Pointer Register, Then Writing Data to the Selected Register

5692-023

SDA

FRAME 1

SLAVE ADDRESS BYTE

FRAME 2

ADDRESS POINTER BYTE

SCL

ACK. BY

AD5100

ACK. BY

AD5100

STOP BY

MASTER

START BY

MASTER

AD0

R/W

OTP

AP6

AP5

AP4

AP3

AP2

AP1

AP0

Figure 22. Dummy Write to Set Proper Address Pointer

5692-024

SDA

FRAME 1

SLAVE ADDRESS BYTE

FRAME 2

READ DATA BYTE

SCL

ACK. BY

AD5100

NO ACK. BY

MASTER

STOP BY

MASTER

START BY

MASTER

AD0

R/W

OTP

Figure 23. Read Data from the Address Pointer Register

AD5100

Rev. A | Page 28 of 36

TEMPORARY OVERRIDE OF DEFAULT SETTINGS

Even with OTP-Programmed parts, it is possible to temporarily

override the default values of any of the permanently program-

mable registers. To override a permanent setting in a particular

should be used:

1. Set Bit 3 = 1 in Register 0x16 (special function 1).

2. Write the desired temporary data to the register of choice.

While the override bit (Bit 3) is set in Register 0x16, the user

can override any registers by simply writing to them with new data.

To reset an overridden register to its default setting, the

following sequence should be used:

1. Set Bit 3 = 0 in Register 0x16.

2. Write a dummy byte to the register of choice.

Clearing the override bit in Register 0x16 does not cause all

overridden registers to revert to their defaults at the same time.

For example, imagine that the user overrides Register 0x01,

If the user subsequently clears the override bit in Register 0x16

and writes a dummy byte to Register 0x01, Register 0x01 reverts

to its default value. However, Register 0x02 and Register 0x03

still contain their override data. To revert both registers to their

default values, the user must write dummy data to each register

individually.

Power cycling the AD5100 also resets all registers to their

programmed defaults.

AD5100

Rev. A | Page 29 of 36

APPLICATIONS INFORMATION

CAR BATTERY AND INFOTAINMENT SYSTEM

SUPPLY MONITORING

The AD5100 has two high voltage monitoring inputs with shut-

down and reset controls over external devices. For example, the

V1MON and V2MON can be used to monitor the signals from

a car battery and an ignition key in an automobile, respectively

(see Figure 24). The shutdown output can be connected to the

shutdown pin of an external regulator to prevent false condi-

tions such as a weak battery or overcharging of a battery by an

alternator. The reset output can be used to reset the processor in

the event of a hardware or software malfunction. An example of

the input and output responses of this circuit is shown in Figure 25.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P37

AD5100YRQZ-1RL7

Mfr. #:

Buy AD5100YRQZ-1RL7

Manufacturer:

Analog Devices Inc.

Description:

Supervisory Circuits System-Mgmt IC w/ Prog VTG Monitor

Lifecycle:

New from this manufacturer.

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AD5100YRQZ-1RL7

AD5100YRQZ-1RL7

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