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9LPRS477CKLFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
IDT
®
Programmable System Clock Chip for ATI RD790-K8
TM
Based Systems 1393—01/28/14
9LPRS477C
Programmable System Clock Chip for ATI RD790 - K8
TM
based Systems
10
SMBus Table: Latched Input Readback Output Enable Control Register
Byte 0 Name Description Type 0 1 Default
Bit 7
SEL_HTT66 readback Hypertransport Select
R
100MHz Diff erential HTT clock
66 MHz 3.3V Single-ended HTT
clock
Latch
Bit 6
SEL_SATA readback SATA Select
R
SRC6/SA TA pair is SRC SS
capable output
SRC6/SATA pair is SATA non-
spread output
Latch
Bit 5
REF0_OE Output Enable RW
Hi-Z
Ena b led 1
Bit 4
REF1_OE Output Enable RW
Hi-Z
Ena b led 1
Bit 3
REF2_OE Output Enable RW
Hi-Z
Ena b led 1
Bit 2
48MHz_1_OE Output Enable RW Low Enabled 1
Bit 1
48MHz_0_OE Output Enable RW Low Enabled 1
Bit 0
SEL_CPU1 readback CPU1/SRC7 Select
R
CPU1 Dif f er ential output SRC7 Dif f er ential output Latc h
SMBus Table:Output Enable Control Register
Byte 1 Name Control Function Type 0 1 Default
Bit 7
SEL_DOC readbac k DOC Selec t
R
SRC5 Dif f erential output DOC Latc h
Bit 6
SRC6/SATA_OE Enable Output Enable RW Low /Low Enabled 1
Bit 5
SRC5_OE Output Enable RW Low /Low Enabled 1
Bit 4
SRC4_OE Output Enable RW Low /Low Enabled 1
Bit 3
SRC3_OE Output Enable RW Low /Low Enabled 1
Bit 2
SRC2_OE Output Enable RW Low /Low Enabled 1
Bit 1
SRC1_OE Output Enable RW Low /Low Enabled 1
Bit 0
SRC0_OE Output Enable RW Low /Low Enabled 1
SMBus Table: Output Enable and 48MHz Strength Control Register
Byte 2 Name Control Function Type 0 1 Default
Bit 7
SB_SRC1_OE Output Enable RW Low /Low Enabled 1
Bit 6
SB_SRC0_OE Output Enable RW Low /Low Enabled 1
Bit 5
ATIG3_OE Output Enable RW Low /Low Enabled 1
Bit 4
ATIG2_OE Output Enable RW Low /Low Enabled 1
Bit 3
ATIG1_OE Output Enable RW Low /Low Enabled 1
Bit 2
ATIG0_OE Output Enable RW Low /Low Enabled 1
Bit 1
48MHz_1_Strength 48MHz_1 Drive Strength Sel. RW 1 Load 2 Load 1
Bit 0
48MHz_0_Strength 48MHz_0 Drive Strength Sel. RW 1 Load 2 Load 1
SMBus Table: CPU/HTT Frequency Control Register
Byte 3 Name Control Function Type 0 1 Default
Bit 7
CPU1_OE/SRC7_OE Output enable RW Low /Low Enable 1
Bit 6
CPU0_OE Output enable RW Low /Low Enable 1
Bit 5
CPU Spread Source CPU Spread Source RW Fix PLL SB_SRC PLL 1
Bit 4
CPU_FS4 CPU Frequency Select MSB RW 0
Bit 3
CPU_FS3 CPU Frequency Select RW 1
Bit 2
CPU_FS2 CPU Frequency Select RW 1
Bit 1
CPU_FS1 CPU Frequency Select RW 1
Bit 0
CPU_FS0 CPU Frequency Select LSB RW 1
SMBus Table: SRC Frequency Control Register
Byte 4 Name Control Function Type 0 1 Default
Bit 7
REF0_Strength REF0_Drive Strength Sel RW 1 Load 2 Load 1
Bit 6
REF1_Strength REF1_Drive Strength Sel RW 1 Load 2 Load 1
Bit 5
REF2_Strength REF2_Drive Strength Sel RW 1 Load 2 Load 1
Bit 4
0
Bit 3
SRC_FS3 SRC Frequency Select RW 1
Bit 2
SRC_FS2 SRC Fr equenc y Select RW 1
Bit 1
SRC_FS1 SRC Frequency Select RW 1
Bit 0
SRC_FS0 SRC Frequency Select LSB RW 1
See CPU Frequency Select Table
Default value corresponds to 200MHz.
Note that Selected HTT frequency tracks the CPU frequency.
Res erv ed
See SRC Frequency Select Table
IDT
®
Programmable System Clock Chip for ATI RD790-K8
TM
Based Systems 1393—01/28/14
9LPRS477C
Programmable System Clock Chip for ATI RD790 - K8
TM
based Systems
11
SMBus Table: ATIG Frequency Select Register
Byte 5 Name Control Function Type 0 1 Default
Bit 7
ATIG PLL TBEN ATIG PLL Turbo Enable RW Disable Enable 0
Bit 6
CPU PLL TBEN CPU PLL Tur bo Enable RW Dis able Enable 0
Bit 5
SRC PLL TBEN SRC PLL Turbo Enable RW Disable Enable 0
Bit 4
DISA BLE_ORT
Disable
O
vershoot
R
eduction
T
echnology during CPU PLL M/N
Programming
RW ENABLE ORT DISABLE ORT 0
Bit 3
ATIG_FS3 ATIG Frequency Select RW 1
Bit 2
ATIG_FS2 ATIG Frequency Select RW 1
Bit 1
ATIG_FS1 ATIG Frequency Select RW 1
Bit 0
ATIG_FS0 ATIG Frequency Select LSB RW 1
SMBus Table: SB_SRC Frequency Select Register
Byte 6 Name Control Function Type 0 1 Default
Bit 7
ATIG SSEN ATIG Spread Enable RW Disable Enable 0
Bit 6
SB_SRC/CPU SSEN SB_SRC/CPU Spread Enable RW Disable Enable 0
Bit 5
SRC SSEN SRC Spread Enable RW Disable Enable 0
Bit 4
SB_SRC_FS4 SB_SRC Frequency Select MSB RW 0
Bit 3
SB_SRC_FS3 SB_SRC Frequency Select RW 1
Bit 2
SB_SRC_FS2 SB_SRC Frequency Select RW 1
Bit 1
SB_SRC_FS1 SB_SRC Frequency Select RW 1
Bit 0
SB_SRC_FS0 SB_SRC Frequency Select LSB RW 1
SMBus Table: Device ID register
Byte 7 Name Control Function Type 0 1 Default
Bit 7
Device ID7 R x
Bit 6
Device ID6 R x
Bit 5
Device ID5 R x
Bit 4
Device ID4 R x
Bit 3
Device ID3 R x
Bit 2
Device ID2 R x
Bit 1
Device ID1 R x
Bit 0
Device ID0 R x
SMBus Table: Vendor & Revision ID Register
Byte 8 Name Control Function Type 0 1 Default
Bit 7
RID3 R - - 0
Bit 6
RID2 R - - 0
Bit 5
RID1 R - - 1
Bit 4
RID0 R - - 1
Bit 3
VID3 R - - 0
Bit 2
VID2 R - - 0
Bit 1
VID1 R - - 0
Bit 0
VID0 R - - 1
SMBus Table: WatchDog Timer Control Register
Byte 9 Name Control Function Type 0 1 Default
Bit 7
HWD_EN Watchdog Har d A larm Enable RW
Disable and Reload Hartd
Alarm Timer, Clear WD Hard
status bit.
Ena b le Time r 0
Bit 6
SWD_EN Watchdog Soft Alarm Enable RW Disable Enable 0
Bit 5
WD Hard Status WD Hard Alarm Status R Normal Alarm X
Bit 4
WD Sof t Status WD Sof t Alarm Status R Normal Alarm X
Bit 3
WDTCtrl
Watch Dog Alarm Time base
Control
RW 290ms Base 1160ms Base 0
Bit 2
HWD2 WD Hard A lar m Timer Bit 2 RW 1
Bit 1
HWD1 WD Hard A lar m Timer Bit 1 RW 1
Bit 0
HWD0 WD Hard A lar m Timer Bit 0 RW 1
V ENDOR ID
REV ISION ID
See ATIG Frequency Select Table
These bits represent the number of Watch Dog Time Base Units
that pass before the Watch Alarm expires. Default is 7 X
290ms = 2s.
Device ID 75 hex for 9LPRS477
See SB_SRC Frequency Select Table
Note: SB_SRC and CPU Clocks are synchronous. Changing this
frequency w ill alter the SB_SRC and CPU f requency by the
same percentage.
IDT
®
Programmable System Clock Chip for ATI RD790-K8
TM
Based Systems 1393—01/28/14
9LPRS477C
Programmable System Clock Chip for ATI RD790 - K8
TM
based Systems
12
SMBus Table: WD Timer Safe Frequency Control Register
Byte 10 Name Control Function Type 0 1 Default
Bit 7
SWD2 WD Sof t A lar m Timer Bit 2 RW 1
Bit 6
SWD1 WD Sof t A lar m Timer Bit 1 RW 1
Bit 5
SWD0 WD Sof t A lar m Timer Bit 0 RW 1
Bit 4
WD SF4 RW 0
Bit 3
WD SF3 RW 1
Bit 2
WD SF2 RW 1
Bit 1
WD SF1 RW 1
Bit 0
WD SF0 RW 1
SMBus Table: Byte Count Register
Byte 11 Name Control Function Type 0 1 Default
Bit 7
0
Bit 6
0
Bit 5
BC5 Byte Count bit 5 (MSB) RW 0
Bit 4
BC4 Byte Count bit 4 RW 0
Bit 3
BC3 Byte Count bit 3 RW 1
Bit 2
BC2 Byte Count bit 2 RW 1
Bit 1
BC1 Byte Count bit 1 RW 1
Bit 0
BC0 Byte Count bit 0 (LSB) RW 1
SMBus Table: M/N Programming Enable and I/O Vout Control Register
Byte 12 Name Control Function Type 0 1 Default
Bit 7
CPU M/N En CPU PLL M/N Prog. Enable RW M/N Prog. Dis abled M/N Pr og. Enabled 0
Bit 6
SRC M/N En SRC M/N Prog.Enable RW M/N Prog. Dis abled M/N Pr og. Enabled 0
Bit 5
A TIG M/N En A TIG M/N Pr og. Enable RW M/N Pr og. Dis abled M/N Pr og. Enabled 0
Bit 4
SB_SRC M/N En SB_SRC M/N Prog. Enable RW M/N Prog. Disabled M/N Prog. Enabled 0
Bit 3
SEL_OC_MODE readback OC MODE Select
R
PCIE Gen2 Mode PCIE Gen1 Mode Latch
Bit 2
IO_V OUT2
IO Output Voltage Select (Most
Signif icant Bit)
RW 1
Bit 1
IO_VOUT1 IO Output Voltage Select RW 0
Bit 0
IO_V OUT0
IO Output Voltage Select (Least
Signif icant Bit)
RW 1
Bytes 13/14 are reserved
SMBus Table:Test Mode Register
Byte 15 Name Control Function Type 0 1 Default
Bit 7
Test_Sel Selects Test Mode
RW
Normal mode All ouputs are REF/N 0
Bit 6
SB_SRC Source SB_SRC Source Selection RW SB_SRC PLL SRC PLL 1
Bit 5
ATIG PLL ATIG PLL DOC pin c ontrol RW DOC0 DOC1 0
Bit 4
CPU PL L CPU PL L DOC p in c o n t r ol RW DOC0 DOC1 0
Bit 3
SRC PLL SRC PLL DOC pin c ontrol RW DOC0 DOC1 0
Bit 2
ATIG PLL ATIG PLL DOC0 2 pin control RW Disable Enable 0
Bit 1
CPU PLL CPU PLL DOC0 2 pin contr ol RW Dis able Enable 0
Bit 0
SRC PLL SRC PLL DOC0 2 pin c ontr ol RW Dis able Enable 0
SMBus Table: CPU PLL Frequency Control Register
Byte 16 Name Control Function Type 0 1 Default
Bit 7
N Div 2 N Div ider Prog bit 2 RW X
Bit 6
N Div 1 N Div ider Prog bit 1 RW X
Bit 5
M Div 5 RW X
Bit 4
M Div 4 RW X
Bit 3
M Div 3 RW X
Bit 2
M Div 2 RW X
Bit 1
M Div 1 RW X
Bit 0
M Div 0 RW X
Watch Dog Safe Freq Programming
bits
M Divider Programming bits
The decimal representation of M and N Divider in Byte 16 and 17
w ill configure the VCO f requency. Default at pow er up = Byte
3 Rom table. See M/N Caculation Tables f or VCO frequency
formulas.
Determines the number of bytes that are read back f rom the
device. Default is 0F hex.
These bits represent the number of Watch Dog Time Base Units
that pass before the Watch Alarm expires. Default is 7 X
290ms = 2s.
Res erv ed
These bits conf igure the safe frequency that the device
returns to if the Watchdog Timer expires. The value show here
corresponds to the pow er up default of the device. See the
various Frequency Select Tables for the exact frequencies.
See Table 5: V_IO Selection
(Def ault is 0.8V )
Res erv ed
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

9LPRS477CKLFT

Mfr. #:
Buy 9LPRS477CKLFT
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner Program Syst CLK ATI RS790 - K8
Lifecycle:
New from this manufacturer.
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