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9LPRS477CKLFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
IDT
®
Programmable System Clock Chip for ATI RD790-K8
TM
Based Systems 1393—01/28/14
9LPRS477C
Programmable System Clock Chip for ATI RD790 - K8
TM
based Systems
16
SMBUS Table: CPU PLL DOC 3 N programming Register (1 pin control : DOC = 1; 2 pin control : DOC [0:1] = 11)
Byte 34 Name Control Function Type 0 1 Default
Bit 7
N Div 10 RW X
Bit 6
N Div 9 RW X
Bit 5
N Div 8 RW X
Bit 4
N Div 7 RW X
Bit 3
N Div 6 RW X
Bit 2
N Div 5 RW X
Bit 1
N Div 4 RW X
Bit 0
N Div 3 RW X
SMBUS Table: ATIG PLL DOC 1 N programming Register (1 pin control : DOC = 1; 2 pin control : DOC [0:1] = 01)
Byte 35 Name Control Function Type 0 1 Default
Bit 7
N Div 10 RW X
Bit 6
N Div 9 RW X
Bit 5
N Div 8 RW X
Bit 4
N Div 7 RW X
Bit 3
N Div 6 RW X
Bit 2
N Div 5 RW X
Bit 1
N Div 4 RW X
Bit 0
N Div 3 RW X
SMBUS Table: ATIG PLL DOC 2 N programming Register (1 pin control : DOC = 1; 2 pin control : DOC [0:1] = 10)
Byte 36 Name Control Function Type 0 1 Default
Bit 7
N Div 10 RW X
Bit 6
N Div 9 RW X
Bit 5
N Div 8 RW X
Bit 4
N Div 7 RW X
Bit 3
N Div 6 RW X
Bit 2
N Div 5 RW X
Bit 1
N Div 4 RW X
Bit 0
N Div 3 RW X
SMBUS Table: ATIG PLL DOC 3 N programming Register (1 pin control : DOC = 1; 2 pin control : DOC [0:1] = 11)
Byte 37 Name Control Function Type 0 1 Default
Bit 7
N Div 10 RW X
Bit 6
N Div 9 RW X
Bit 5
N Div 8 RW X
Bit 4
N Div 7 RW X
Bit 3
N Div 6 RW X
Bit 2
N Div 5 RW X
Bit 1
N Div 4 RW X
Bit 0
N Div 3 RW X
SMBUS Table: SRC PLL DOC 1 N programming Register (1 pin control : DOC = 1; 2 pin control : DOC [0:1] = 01)
Byte 38 Name Control Function Type 0 1 Default
Bit 7
N Div 10 RW X
Bit 6
N Div 9 RW X
Bit 5
N Div 8 RW X
Bit 4
N Div 7 RW X
Bit 3
N Div 6 RW X
Bit 2
N Div 5 RW X
Bit 1
N Div 4 RW X
Bit 0
N Div 3 RW X
SMBUS Table: SRC PLL DOC 2 N programming Register (1 pin control : DOC = 1; 2 pin control : DOC [0:1] = 10)
Byte 39 Name Control Function Type 0 1 Default
Bit 7
N Div 10 RW X
Bit 6
N Div 9 RW X
Bit 5
N Div 8 RW X
Bit 4
N Div 7 RW X
Bit 3
N Div 6 RW X
Bit 2
N Div 5 RW X
Bit 1
N Div 4 RW X
Bit 0
N Div 3 RW X
N Div ider Progr amming By te20
bit(7:0) and Byte19 bit(7:6)
The decimal representation of M and N Divider in Byte 21 and 38
w ill configure the VCO f requency. Default at pow er up = Byte
4 Rom table. See M/N Caculation Tables f or VCO frequency
formulas.
N Div ider Progr amming By te20
bit(7:0) and Byte19 bit(7:6)
The decimal representation of M and N Divider in Byte 21 and 39
w ill configure the VCO f requency. Default at pow er up = Byte
4 Rom table. See M/N Caculation Tables f or VCO frequency
formulas.
The decimal representation of M and N Divider in Byte 16 and 34
w ill configure the VCO f requency. Default at pow er up = Byte
3 Rom table. See M/N Caculation Tables f or VCO frequency
formulas.
The decimal representation of M and N Divider in Byte 26 and 35
w ill configure the VCO f requency. Default at pow er up = Byte
5 Rom table. See M/N Caculation Tables f or VCO frequency
formulas.
N Div ider Progr amming By te20
bit(7:0) and Byte19 bit(7:6)
The decimal representation of M and N Divider in Byte 26 and 36
w ill configure the VCO f requency. Default at pow er up = Byte
5 Rom table. See M/N Caculation Tables f or VCO frequency
formulas.
N Div ider Progr amming By te20
bit(7:0) and Byte19 bit(7:6)
The decimal representation of M and N Divider in Byte 26 and 37
w ill configure the VCO f requency. Default at pow er up = Byte
5 Rom table. See M/N Caculation Tables f or VCO frequency
formulas.
N Div ider Progr amming By te20
bit(7:0) and Byte19 bit(7:6)
N Div ider Progr amming By te20
bit(7:0) and Byte19 bit(7:6)
IDT
®
Programmable System Clock Chip for ATI RD790-K8
TM
Based Systems 1393—01/28/14
9LPRS477C
Programmable System Clock Chip for ATI RD790 - K8
TM
based Systems
17
SMBUS Table: SRC PLL DOC 3 N programming Register (1 pin control : DOC = 1; 2 pin control : DOC [0:1] = 11)
Byte 40 Name Control Function Type 0 1 Default
Bit 7
N Div 10 RW X
Bit 6
N Div 9 RW X
Bit 5
N Div 8 RW X
Bit 4
N Div 7 RW X
Bit 3
N Div 6 RW X
Bit 2
N Div 5 RW X
Bit 1
N Div 4 RW X
Bit 0
N Div 3 RW X
SMBus Table: ATIG PLL Spread Spectrum Control Register
Byte 41 Name Control Function Type 0 1 Default
Bit 7
SSP7 RW X
Bit 6
SSP6 RW X
Bit 5
SSP5 RW X
Bit 4
SSP4 RW X
Bit 3
SSP3 RW X
Bit 2
SSP2 RW X
Bit 1
SSP1 RW X
Bit 0
SSP0 RW X
SMBus Table: ATIG PLL Spread Spectrum Control Register
Byte 42 Name Control Function Type 0 1 Default
Bit 7
SSP15 RW X
Bit 6
SSP14 RW X
Bit 5
SSP13 RW X
Bit 4
SSP12 RW X
Bit 3
SSP11 RW X
Bit 2
SSP10 RW X
Bit 1
SSP9 RW X
Bit 0
SSP8 RW X
N Div ider Progr amming By te20
bit(7:0) and Byte19 bit(7:6)
The decimal representation of M and N Divider in Byte 21 and 37
w ill configure the VCO f requency. Default at pow er up = Byte
4 Rom table. See M/N Caculation Tables for VCO frequency
formulas.
Spread Spectrum Programming
b(15:8)
These bits set the ATIG spread pecentage.Please contact IDT
for the appropriate values.
Spread Spectrum Programming
b(7:0)
These bits set the ATIG spread pecentage.Please contact IDT
for the appropriate values.
IDT
®
Programmable System Clock Chip for ATI RD790-K8
TM
Based Systems 1393—01/28/14
9LPRS477C
Programmable System Clock Chip for ATI RD790 - K8
TM
based Systems
18
Absolute Maximum Rating
PA RA METER SY MBOL CONDITIONS MIN TY P MA X UNITS Notes
3.3V Core Supply Voltage VDDxxx - 3.3 GND + 3.9V V 1
Storage Temperature Ts - -65 150
°
C1
Ambient Operating Temp Tambient - 0 70 °C 1
Case Temperature Tcase - 115 °C 1
Input ESD protection HBM ESD prot - 2000 V 1
1
Guaranteed by design and characterization, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
PA RA METER SY MBOL CONDITIONS* MIN TY P MAX UNITS Notes
3.3V Core Supply Voltage VDDxxx - 3.135 3.3 3.465 V 1
Input High Voltage V
IH
VDD = 3.3 V +/-5% 2 V
DD
+ 0.3 V 1
Input Low Voltage V
IL
VDD = 3.3 V +/-5% V
SS
- 0.3 0.8 V 1
Input High Current I
IH
V
IN
= V
DD
-5 5 uA 1
I
IL1
V
IN
= 0 V; Inputs w ith no pull-up
resistors
-5 uA 1
I
IL2
V
IN
= 0 V; Inputs w ith pull-up
resistors
-200 uA 1
Low Threshold Input-
High Voltage
V
IH_FS
VDD = 3.3 V +/-5% 0.7 V
DD
+ 0.3 V 1
Low Threshold Input-
Low Voltage
V
IL_FS
VDD = 3.3 V +/-5% V
SS
- 0.3 0.35 V 1
Operating Current I
DD3.3OP
all outputs driven 225 mA 1
Pow erdow n Current I
DD3.3PD
all dif f pairs low /low 12 mA 1
Input Frequency F
i
VDD = 3.3 V +/-5% 14.31818 MHz 2
Pin Inductance L
pin
7nH1
C
IN
Logic Inputs 5 pF 1
C
OUT
Output pin capacitance 6 pF 1
C
INX
X1 & X2 pins 5 pF 1
Clk Stabilization T
STAB
From VDD Pow er-Up or de-
assertion of PD to 1st clock
1.8 ms 1
Modulation Frequency Triangular Modulation 30 33 kHz 1
Tdr iv e_PD
CPU output enable after
PD de-assertion
300 us 1
Tfall_PD PD f all time of 5 ns 1
Trise_PD PD rise time of 5 ns 1
SMBus Voltage V
DDSMB
2.7 5.5 V 1
Low -level Output Voltage V
OLS MB
@ I
PULLUP
0.4 V 1
Current sinking at
V
OL
= 0.4 V
I
PULLUPSMB
46 mA1
SMBCLK/SMBDAT
Cloc k/Data Ris e Time
T
RSMB
(Max VIL - 0.15) to
(Min VIH + 0.15)
1000 ns 1
SMBCLK/SMBDAT
Cloc k/Data Fall Time
T
FSMB
(Min VIH + 0.15) to
(Max VIL - 0.15)
300 ns 1
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
1
Guaranteed by design and characterization, not 100% tested in production.
Input Low Current
Input Capacitance
2
Input frequency should be measured at the REF pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

9LPRS477CKLFT

Mfr. #:
Buy 9LPRS477CKLFT
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner Program Syst CLK ATI RS790 - K8
Lifecycle:
New from this manufacturer.
Delivery:
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