CAT5411
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7
VALID IN
HIZ
HIZ
SCK
SI
SO
Figure 2. Synchronous Data Timing
t
DIS
t
CSH
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
CS
t
CSS
V
OH
V
OL
t
CS
t
HO
t
WL
t
V
t
RI
t
FI
t
SU
t
H
t
WH
Figure 3. HOLD Timing
SCK
SO
HIGH IMPEDANCE
t
LZ
t
HD
t
CD
t
HD
t
CD
t
HZ
HOLD
CS
CAT5411
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INSTRUCTION AND REGISTER DESCRIPTION
Device Type/Address Byte
The first byte sent to the CAT5411 from the master/
processor is called the Device Address Byte. The most
significant four bits of the Device Type address are a device
type identifier. These bits for the CAT5411 are fixed at
0101[B] (refer to Figure 4).
The two least significant bits in the slave address byte, A1
A0, are the internal slave address and must match the
physical device address which is defined by the state of the A1
A0 input pins for the CAT5411 to successfully continue the
command sequence. Only the device which slave address
matches the incoming device address sent by the master
executes the instruction. The A1 A0 inputs can be actively
driven by CMOS input signals or tied to V
CC
or V
SS
. The
remaining two bits in the device address byte must be set to 0.
Instruction Byte
The next byte sent to the CAT5411 contains the instruction
and register pointer information. The four most significant
bits used provide the instruction opcode I [3:0]. The R1 and
R0 bits point to one of the four data registers of each
associated potentiometer. The least two significant bits point
to one of two Wiper Control Registers. The format is shown
in Figure 5.
Table 11. DATA REGISTER SELECTION
Data Register Selected R1 R0
DR0 0 0
DR1 0 1
DR2 1 0
DR3 1 1
Figure 4. Identification Byte Format 0101 Device Type Identifier (MSB)
ID3 ID2 ID1 ID0 0 0 A1 A0
0101
(MSB) (LSB)
Device Type Identifier
Slave Address
Figure 5. Instruction Byte Format
I3 I2 I1 I0 R1 R0 0 P0
(MSB) (LSB)
Instruction Opcode
Data Register Selection
WCR/Pot Selection
Figure 6. Potentiometer Timing (for All Load Instructions)
SCK
SI
LSBMSB
SO
High Impedance
CS
V
W
/R
W
. . .
. . .
t
WRL
WIPER CONTROL AND DATA REGISTERS
Wiper Control Register (WCR)
The CAT5411 contains two 6-bit Wiper Control
Registers, one for each potentiometer. The Wiper Control
Register output is decoded to select one of 64 switches along
its resistor array. The contents of the WCR can be altered in
four ways: it may be written by the host via Write Wiper
Control Register instruction; it may be written by
transferring the contents of one of four associated Data
Registers via the XFR Data Register instruction, it can be
modified one step at a time by the Increment/Decrement
instruction (see Instruction section for more details).
Finally, it is loaded with the content of its data register zero
(DR0) upon power-up.
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The Wiper Control Register is a volatile register that loses
its contents when the CAT5411 is powered-down. Although
the register is automatically loaded with the value in DR0
upon power-up, this may be different from the value present
at power-down.
Data Registers (DR)
Each potentiometer has four 6-bit non-volatile Data
Registers. These can be read or written directly by the host.
Data can also be transferred between any of the four Data
Registers and the associated Wiper Control Register. Any
data changes in one of the Data Registers is a non-volatile
operation and will take a maximum of 5 ms.
Write in Process
The contents of the Data Registers are saved to
nonvolatile memory when the CS
input goes HIGH after a
write sequence is received. The status of the internal write
cycle can be monitored by issuing a Read Status command
to read the Write in Process (WIP) bit.
INSTRUCTIONS
Four of the ten instructions are three bytes in length. These
instructions are:
Read Wiper Control Register – read the current wiper
position of the selected potentiometer in the WCR
Write Wiper Control Register – change current wiper
position in the WCR of the selected potentiometer
Read Data Register – read the contents of the selected
Data Register
Write Data Register – write a new value to the
selected Data Register
Read Status – Read the status of the WIP bit which
when set to “1” signifies a write cycle is in progress.
Table 12. INSTRUCTION SET (Note: 1/0 = data is one or zero)
Instruction
Instruction Set
Operations
I3 I2 I1 I0 R1 R0 0 WCR
0
/ P0
Read Wiper Control Register 1 0 0 1 0 0 0 1/0 Read the contents of the Wiper Control
Register pointed to by P0
Write Wiper Control Register 1 0 1 0 0 0 0 1/0 Write new value to the Wiper Control Register
pointed to by P0
Read Data Register 1 0 1 1 1/0 1/0 0 1/0 Read the contents of the Data Register pointed
to by P0 and R1R0
Write Data Register 1 1 0 0 1/0 1/0 0 1/0 Write new value to the Data Register pointed
to by P0 and R1R0
XFR Data Register to Wiper
Control Register
1 1 0 1 1/0 1/0 0 1/0 Transfer the contents of the Data Register
pointed to by P0 and R1R0 to its associated
Wiper Control Register
XFR Wiper Control Register
to Data Register
1 1 1 0 1/0 1/0 0 1/0 Transfer the contents of the Wiper Control
Register pointed to by P0 to the Data Register
pointed to by R1R0
Global XFR Data Registers
to Wiper Control Registers
0 0 0 1 1/0 1/0 0 0 Transfer the contents of the Data Registers
pointed to by R1R0 of all four pots to their
respective Wiper Control Registers
Global XFR Wiper Control
Registers to Data Register
1 0 0 0 1/0 1/0 0 0 Transfer the contents of both Wiper Control
Registers to their respective data Registers
pointed to by R1R0 of all four pots
Increment/Decrement
Wiper Control Register
0 0 1 0 0 0 0 1/0 Enable Increment/decrement of the Control
Latch pointed to by P0
Read Status 0 1 0 1 0 0 0 1 Read WIP bit to check internal write cycle
status
The basic sequence of the three byte instructions is
illustrated in Figure 8. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. The WCR controls the position of the wiper. The
response of the wiper to this action will be delayed by t
WRL
.
A transfer from the WCR (current wiper position), to a Data
Register is a write to non-volatile memory and takes a
minimum of t
WR
to complete. The transfer can occur
between one of the four potentiometers and one of its
associated registers; or the transfer can occur between all
potentiometers and one associated register.
Four instructions require a two-byte sequence to
complete, as illustrated in Figure 7. These instructions
transfer data between the host/processor and the CAT5411;
either between the host and one of the data registers or
directly between the host and the Wiper Control Register.
These instructions are:

CAT5411YI10

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Digital Potentiometer ICs DPP NV Dual 64 taps SPI
Lifecycle:
New from this manufacturer.
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