MAX9386/MAX9387/MAX9388
Detailed Description
The MAX9386/MAX9387/MAX9388 are fully differential,
high-speed, and low-jitter ECL/PECL muxes with output
buffer(s). The devices are designed for clock-and-data
distribution applications, and feature extremely low
propagation delays (318ps, typ) and output-to-output
skews (3.9ps, typ). The MAX9386 is a 5:1 mux with a
single output buffer. The MAX9387 is a 5:1 mux with
dual output buffers, and is intended for use in redun-
dant systems. The MAX9388 is a 4:1 mux with a single
output buffer, and is pin compatible with the
MC100EP57.
Three single-ended select inputs, SEL0, SEL1, and
SEL2, control the mux function on the MAX9386/
MAX9387. The MAX9388 has two select inputs, SEL0
and SEL1 (see Tables 1 and 2). The mux select inputs
are compatible with ECL/PECL logic, and are internally
referenced to the on-chip output V
BB,
nominally V
CC
-
1.425V. The select inputs accept signals between V
CC
and V
EE
. Internal 120k pulldowns to V
EE
ensure a low
default condition if the select inputs are left open,
selecting the D0, D0 input.
The differential inputs D, D can be configured to accept
a single-ended signal when the unused complementary
input is connected to the on-chip reference voltage
V
BB.
The reference output voltages, V
BB1
and V
BB2,
provide the reference voltage for single-ended opera-
tion for each mux. A single-ended input of at least V
BB
_
±100mV or a differential input of at least 100mV switches
the outputs to the V
OH
and V
OL
levels specified in the
DC Electrical Characteristics. The maximum magnitude
of the differential input from D to D is ±3.0V. This limit
also applies to the difference between a single-ended
input and any reference voltage input.
Specifications for the high and low voltages of a differ-
ential input (V
IHD
and V
ILD
) and the differential input
voltage (V
IHD
- V
ILD
) apply simultaneously.
Single-Ended Operation
The recommended supply voltage for single-ended
operation is 3.0V to 5.5V. The differential inputs (D, D)
can be configured to accept single-ended inputs when
operating at supply voltages greater than 2.725V. In
single-ended mode operation, the unused complemen-
tary input needs to be connected to the on-chip refer-
ence voltage, V
BB
, as a reference. For example, the
differential D, D input is converted to a noninverting,
single-ended input by connecting V
BB
to D and con-
necting the single-ended input to D. Similarly, an invert-
ing input is obtained by connecting V
BB
to D and
connecting the single-ended input to D. With a differen-
tial input configured as single ended (using V
BB
), the
single-ended input can be driven to V
CC
or V
EE
or with
a single-ended LVPECL/LVECL signal.
In single-ended mode operation, a user must ensure
that the supply voltage (V
CC
- V
EE
) is greater than
2.725V. This is because the input high minimum level
must be at (V
EE
+ 1.2V) or higher for proper operation.
The reference voltage, V
BB
, must be at least (V
EE
+
1.2V) for the same reason because it becomes the high-
level input when a single-ended input swings below it.
The minimum V
BB
output for the MAX9386/MAX9387/
MAX9388 is (V
CC
- 1.38V). Substituting the minimum
V
BB
output for (V
BB
= V
EE
+ 1.2V) results in a minimum
supply (V
CC
- V
EE
) of 2.725V. Rounding up to standard
supplies gives the recommended single-ended operat-
ing supply ranges (V
CC
- V
EE
) of 3.0V to 5.5V.
When using the V
BB
reference output, bypass it with a
0.01µF ceramic capacitor to V
CC
. If not used, leave it
open. The V
BB
reference can source or sink a total of
0.5mA (shared between V
BB1
and V
BB2
), which is suffi-
cient to drive five inputs.
Differential 5:1 or 4:1 ECL/PECL Multiplexers
with Single/Dual Output Buffers
10 ______________________________________________________________________________________
Table 1. Mux Select Input Truth Table for
MAX9386/MAX9387
SEL2 SEL1 SEL0
DATA OUTPUT
L or open
L or open L or open
D0*
L or open
L or open
HD1
L or open
H
L or open
D2
L or open
HH D3
HXX D4
*Default output when SEL0, SEL1, and SEL2 are left open.
SEL1 SEL0
DATA OUTPUT
L or open L or open D0*
L or open H D1
H L or open D2
HHD3
*Default output when SEL0 and SEL1 are left open.
Table 2. Mux Select Input Truth Table for
MAX9388
Applications Information
Output Termination
Terminate the outputs through 50 to V
CC
- 2V or use
equivalent Thevenin terminations. Terminate each Q
and Q output with identical termination on each for min-
imal distortion. When a single-ended signal is taken
from the differential output, terminate both Q and Q.
Ensure that output currents do not exceed the current
limits as specified in the Absolute Maximum Ratings
table. Under all operating conditions, the devices total
thermal limits should be observed.
Supply Bypassing
Bypass V
CC
to V
EE
with high-frequency surface-mount
ceramic 0.1µF and 0.01µF capacitors. For PECL, bypass
each V
CC
to V
EE
. For ECL, bypass each V
EE
to V
CC
.
Place the capacitors as close to the device as possible
with the 0.01µF capacitor closest to the device pins.
Use multiple vias when connecting the bypass capaci-
tors to ground. When using the V
BB1
or V
BB2
reference
outputs, bypass each one with a 0.01µF ceramic
capacitor to V
CC
. If the V
BB1
or V
BB2
reference outputs
are not used, they can be left open.
Traces
Circuit board trace layout is very important to maintain
the signal integrity of high-speed differential signals.
Maintaining integrity is accomplished in part by reduc-
ing signal reflections and skew, and increasing com-
mon-mode noise immunity.
Signal reflections are caused by discontinuities in the
50 characteristic impedance of the traces. Avoid dis-
continuities by maintaining the distance between differ-
ential traces, not using sharp corners or using vias.
Maintaining distance between the traces also increases
common-mode noise immunity. Reducing signal skew
is accomplished by matching the electrical length of
the differential traces.
Chip Information
TRANSISTOR COUNT: 583
PROCESS: Bipolar
MAX9386/MAX9387/MAX9388
Differential 5:1 or 4:1 ECL/PECL Multiplexers
with Single/Dual Output Buffers
______________________________________________________________________________________ 11
V
BB1
V
BB2
V
CC
V
EE
V
CC
V
EE
MUX
150k
150k120k 150k
250k
D0
D0
D1
D1
D2
D2
D3
D3
D4**
SEL0
SEL1
SEL2**
D4**
Q0 (Q*)
Q0 (Q*)
MAX9386 (*) DOES NOT HAVE Q1 AND Q1 OUTPUTS, AND
MAX9388 (**) DOES NOT HAVE D4, D4, AND SEL2 INPUTS.
Q1*
Q1*
D_
D_
MAX9386
MAX9387
MAX9388
V
EE
Functional Block Diagram
Ordering Information (continued)
PART
TEMP
RANGE
PIN-
PACKAGE
SELECTION
MAX9387EUG
-40°C to +85°C 24 TSSOP
5:1 mux with 2
output buffers
M AX 9387E E G *
-40°C to +85°C 24 QSOP
5:1 mux with 2
output buffers
MAX9388EUP
-40°C to +85°C 20 TSSOP
4:1 mux with 1
output buffer
MAX9388EEP*
-40°C to +85°C 20 QSOP
4:1 mux with 1
output buffer
*Future product—contact factory for availability.
MAX9386/MAX9387/MAX9388
Differential 5:1 or 4:1 ECL/PECL Multiplexers
with Single/Dual Output Buffers
12 ______________________________________________________________________________________
TOP VIEW
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
V
CC
SEL1
SEL0
V
CC
D1
D1
DO
V
CC
DO
Q
Q
V
CC
V
BB1
D3
D3
D2
D2
12
11
9
10
V
BB2
V
EE
V
EE
MAX9388
1
2
3
4
5
6
7
8
V
CC
SEL2
SEL1
SEL0
D1
D1
DO
DO
V
CC
Q0
Q0
V
CC
V
BB1
D3
D3
D2
D2
9
10
V
BB2
V
EE
D4
D4
MAX9387
TSSOP/QSOP
TSSOP/QSOP
Q1
Q1
14
13
11
12V
EE
24
23
22
21
20
19
18
17
16
15
Pin Configurations (continued)

MAX9387EUG+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Clock Drivers & Distribution Differential 5:1 or 4:1 ECL/PECL Multiplexers with Single/Dual Output Buffers
Lifecycle:
New from this manufacturer.
Delivery:
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