V
CC
Positive Supply. Bypass each V
CC
to V
EE
with 0.1µF and 0.01µF ceramic capacitors. Place the capacitors
as close to the device as possible with the smaller value capacitor closest to the device.
2 D0 Noninverting Differential Input 0. Internal 250kΩ to V
CC
and 150kΩ to V
EE
.
3 D0 Inverting Differential Input 0. Internal 150kΩ to V
CC
and 150kΩ to V
EE
.
4 D1 Noninverting Differential Input 1. Internal 250kΩ to V
CC
and 150kΩ to V
EE
.
5 D1 Inverting Differential Input 1. Internal 150kΩ to V
CC
and 150kΩ to V
EE
.
6 D2 Noninverting Differential Input 2. Internal 250kΩ to V
CC
and 150kΩ to V
EE
.
7 D2 Inverting Differential Input 2. Internal 150kΩ to V
CC
and 150kΩ to V
EE
.
8 D3 Noninverting Differential Input 3. Internal 250kΩ to V
CC
and 150kΩ to V
EE
.
9 D3 Inverting Differential Input 3. Internal 150kΩ to V
CC
and 150kΩ to V
EE
.
10 D4 Noninverting Differential Input 4. Internal 250kΩ to V
CC
and 150kΩ to V
EE
.
11 D4 Inverting Differential Input 4. Internal 150kΩ to V
CC
and 150kΩ to V
EE
.
12, 13 V
EE
Negative Supply
14 V
BB2
Reference Output Voltage 2. Connect to the inverting or noninverting data input to provide a reference for
single-ended operation. When used, bypass V
BB2
to V
CC
with a 0.01µF ceramic capacitor. Otherwise
leave open.
15 V
BB1
Reference Output Voltage 1. Connect to the inverting or noninverting data input to provide a reference for
single-ended operation. When used, bypass V
BB1
to V
CC
with a 0.01µF ceramic capacitor. Otherwise
leave open.
16 Q1 Inverting Output 1. Typically terminate with 50Ω resistor to V
CC
- 2V.
17 Q1 Noninverting Output 1. Typically terminate with 50Ω resistor to V
CC
- 2V.
19 Q0 Inverting Output 0. Typically terminate with 50Ω resistor to V
CC
- 2V.
20 Q0 Noninverting Output 0. Typically terminate with 50Ω resistor to V
CC
- 2V.
21 SEL0 Select Logic Input 0. Internal 120kΩ pulldown to V
EE
.
22 SEL1 Select Logic Input 1. Internal 120kΩ pulldown to V
EE
.
23 SEL2 Select Logic Input 2. Internal 120kΩ pulldown to V
EE
.
