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IS61C64AL ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
7
Rev. B
10/23/06
AC WAVEFORMS
WRITE CYCLE NO. 1 (
WEWE
WEWE
WE Controlled)
(1,2)
DATA UNDEFINED
t WC
VALID ADDRESS
t SCS
t PWE1
t PWE2
t AW
t HA
HIGH-Z
t HD
t SA
t HZWE
ADDRESS
CE
WE
D
OUT
DIN
DATA
IN VALID
t LZWE
t SD
CE_WR1.eps
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range)
-10 ns -12 ns
Symbol Parameter Min. Max Min. Max. Unit
tWC Write Cycle Time 10 — 12 — ns
tSCS CE to Write End 9 — 10 — ns
tAW Address Setup Time 9 — 10 — ns
to Write End
tHA Address Hold 0 — 0 — ns
from Write End
tSA Address Setup Time 0 — 0 — ns
tPWE1 WE Pulse Width (OE LOW) 9 — 9 — ns
tPWE2 WE Pulse Width (OE HIGH) 8 — 8 — ns
tSD Data Setup to Write End 7 — 7 — ns
tHD Data Hold from Write End 0 — 0 — ns
tHZWE
(2)
WE LOW to High-Z Output — 6 — 6 ns
tLZWE
(2)
WE HIGH to Low-Z Output 0 — 0 — ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
