LTC2471/LTC2473
12
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applicaTions inForMaTion
Figure 7. Timing Diagram for Writing to the LTC2471/LTC2473
Data Input Format
After a START condition, the master sends a 7-bit ad
-
dress followed by a read/write request (R/W) bit. The
R/W bit is 0 for a write. The data input word is 4 bits long
and consists of two enable bits (EN1 and EN2) and two
programming bits (SPD and SLP), see Figure 7. EN1 is
applied to the first rising edge of SCL after a valid write
address is acknowledged. Programming is enabled by
setting EN1 = 1 and EN2 = 0.
The speed bit (SPD) determines the output rate, SPD = 0
(default) for a 208sps and SPD = 1 for a 833sps output
rate. The sleep bit (SLP) is used to power down the
on-chip reference. In the default mode, the reference re-
mains powered up at the conclusion of each conversion
cycle while the ADC is automatically powered down at the
end of each conversion cycle. If the SLP bit is set HIGH,
the reference and the ADC are powered down once the next
conversion cycle is completed. The reference and ADC are
powered up again once a valid read/write is acknowledged.
The following conversion is invalid if the next conversion
is started before the reference has started up (see Figure 3
for reference startup times as a function of compensation
capacitor and reference capacitor).
The sleep bit (SLP) is used to power down the on chip
reference. In the default mode, the reference remains
powered up even when the ADC is powered down. If the
SLP bit is set HIGH, the reference will power down after
the next conversion is complete. It will remain powered
down until a valid address is acknowledged. The reference
startup time is approximately 12ms. In order to ensure a
stable reference for the following conversions, either the
data input/output time should be delayed 12ms after an
address acknowledge or the first conversion following a
reference start up should be discarded.
Table 2. Input Data Format
BIT NAME FUNCTION
EN1 Should Be High (EN1 = 1) in Order to Enable Program Mode
EN2 Should Be Low (EN2 = 0) in Order to Enable Program Mode
SPD Low (SPD = 0, Default) for 208sps, High (SPD = 1) for
833sps Output Rate
SLP Low (SLP = 0, Default) for Nap Mode, High (SLP = 1)
for Sleep Mode Where Both Reference and Converter Are
Powered Down
SDA
SCL
EN1 EN2 SPD SLP
W
SLEEP
START BY
MASTER
DATA INPUT
7 8 9
1 2 3 4 5 6 7 8 9
1 2 …
7-BIT ADDRESS
ACK BY
LTC2471/LTC2473
ACK BY
LTC2471/LTC2473
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