LTC2471/LTC2473
9
24713fb
For more information www.linear.com/LTC2471
Ease of Use
The LTC2471/LTC2473 data output has no latency, filter
settling delay, or redundant results associated with the
conversion cycle. There is a one-to-one correspondence
between the conversion and the output data. Therefore,
multiplexing multiple analog input voltages requires no
special actions.
The LTC2471/LTC2473 include a proprietary input sampling
scheme that reduces the average input current by several
orders of magnitude when compared to traditional delta-
sigma architectures. This allows external filter networks
to interface directly to the LTC2471/LTC2473. Since the
average input sampling current is 50nA, an external RC
lowpass filter using 1kΩ and 0.1µF results in <1LSB
additional error. Additionally, there is negligible leakage
current between IN
+
and IN
–
(for the LTC2473).
Input Voltage Range (LTC2471)
Ignoring offset and full-scale errors, the LTC2471 will
theoretically output an “all zero” digital result when the
input is at ground (a zero scale input) and an “all one”
digital result when the input is at V
REF
or higher (V
REFOUT
= 1.25V). In an underrange condition (for all input voltages
below zero scale) the converter will generate the output
code 0. In an overrange condition (for all input voltages
greater than V
REF
) the converter will generate the output
code 65535.
Input Voltage Range (LTC2473)
As detailed in the Output Data Format section, the output
code is given as INT(32767.5 • (V
IN
+
– V
IN
–
)/V
REF
+ 32767.5.
For (V
IN
+
– V
IN
–
) ≥ V
REF
, the output code is clamped at
65535 (all ones). For (V
IN
+
– V
IN
–
) ≤ –V
REF
, the output
code is clamped at 0 (all zeroes).
applicaTions inForMaTion
I
2
C INTERFACE
The LTC2471/LTC2473 communicate through an I
2
C in-
terface. The I
2
C interface is a 2-wire open-drain interface
supporting multiple devices and masters on a single bus.
The connected devices can only pull the data line (SDA)
LOW and can never drive it HIGH. SDA must be externally
connected to the supply through a pull-up resistor. When
the data line is free, it is HIGH. Data on the I
2
C bus can
be transferred at rates up to 100kbits/s in the standard
mode and up to 400kbits/s in the fast mode.
Upon entering the DATA INPUT/OUTPUT state,
SDA
outputs the sign (D15) of the conversion result. During
this state, the ADC shifts the conversion result serially
through the
SDA
output pin under the control of the SCL
input pin. There is no latency in generating this data and
the result corresponds to the last completed conversion.
A new bit of data appears at the
SDA
pin following each
falling edge detected at the SCL input pin and appears
from MSB to LSB. The user can reliably latch this data on
every rising edge of the external serial clock signal driving
the SCL pin.
Each device on the I
2
C bus is recognized by a unique
address stored in that device and can operate either as
a transmitter or receiver, depending on the function of
the device. In addition to transmitters and receivers,
devices can also be considered as masters or slaves when
performing data transfers. A master is the device which
initiates a data transfer on the bus and generates the
clock signals to permit that transfer. Devices addressed
by the master are considered a slave. The address of the
LTC2471/LTC2473 is 0010100 (if A0 is tied to GND) or
1010100 (if A0 is tied to V
CC
).
