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LTC2471IMS#TRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
LTC2471/LTC2473
10
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Figure 5. Definition of Timing for Fast/Standard Mode Devices on the I
2
C Bus
The LTC2471/LTC2473 can only be addressed as a slave.
It can only transmit the last conversion result. The serial
clock line, SCL, is always an input to the LTC2471/LTC2473
and the serial data line SDA is bidirectional. Figure 5 shows
the definition of the I
2
C timing.
The START and STOP Conditions
A START (S) condition is generated by transitioning SDA
from HIGH to LOW while SCL is HIGH. The bus is consid
-
ered to be busy after the START condition. When the data
transfer is finished, a STOP (P) condition is generated by
transitioning SDA from LOW to HIGH while SCL is HIGH.
The bus is free after a STOP is generated. START and STOP
conditions are always generated by the master.
When the bus is in use, it stays busy if a repeated START
(Sr) is generated instead of a STOP condition. The repeated
START timing is functionally identical to the START and
is used for reading from the device before the initiation
of a new conversion.
Data Transferring
After the START condition, the I
2
C bus is busy and data
transfer can begin between the master and the addressed
slave. Data is transferred over the bus in groups of nine
bits, one byte followed by one acknowledge (ACK) bit. The
master releases the SDA line during the ninth SCL clock
cycle. The slave device can issue an ACK by pulling SDA
LOW or issue a Not Acknowledge (NACK) by leaving the
SDA line HIGH impedance (the external pull-up resistor
will hold the line HIGH). Change of data only occurs while
the clock line (SCL) is LOW.
Output Data Format
After a START condition, the master sends a 7-bit address
followed by a read request (R) bit. The bit R is 1 for a
Read Request. If the 7-bit address matches the LTC2471/
LTC2473’s address (0010100 or 1010100, depending on
the state of the pin A0) the ADC is selected. When the
device is addressed during the conversion state, it does
SDA
SCL
S Sr P S
t
HD(STA)
t
HD(DAT)
t
SU(STA)
t
SU(STO)
t
SU(DAT)
t
LOW
t
HD(SDA)
t
SP
t
BUF
t
r
t
f
t
r
t
f
t
HIGH
24713 F05
LTC2471/LTC2473
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Figure 6. Read Sequence Timing Diagram
not accept the request and issues a NACK by leaving the
SDA line HIGH. If the conversion is complete, the LTC2471/
LTC2473 issue an ACK by pulling the SDA line LOW.
Following the ACK, the LTC2471/LTC2473 can output data.
The data output stream is 16 bits long and is shifted out
on the falling edges of SCL (see Figure 6).
The DATA INPUT/OUTPUT state is concluded once all 16
data bits have been read or after a STOP condition.
1 7 8 9 2 31 8
D8D13D14
MSB
D15RSDA
SCL
7-BIT
ADDRESS
START BY
MASTER
D7 D6 D5 D0
LSB
9 1 2 3 8 9
ACK BY
MASTER
NACK BY
MASTER
SLEEP DATA OUTPUT CONVERSION
24713 F06
ACK BY
LTC2471/LTC2473
Table 1. LTC2471/LTC2473 Output Data Format
SINGLE ENDED INPUT V
IN
(LTC2471)
DIFFERENTIAL INPUT VOLTAGE
V
IN
+
– V
IN
–
(LTC2473)
D15
(MSB)
D14 D13 D12...D2 D1 D0
(LSB)
CORRESPONDING
DECIMAL VALUE
≥V
REF
≥V
REF
1 1 1 1 1 1 65535
V
REF
– 1LSB V
REF
– 1LSB 1 1 1 1 1 0 65534
0.75 • V
REF
0.5 • V
REF
1 1 0 0 0 0 49152
0.75 • V
REF
– 1LSB 0.5 • V
REF
– 1LSB 1 0 1 1 1 1 49151
0.5 • V
REF
0 1 0 0 0 0 0 32768
0.5 • V
REF
– 1LSB –1LSB 0 1 1 1 1 1 32767
0.25 • V
REF
–0.5 • V
REF
0 1 0 0 0 0 16384
0.25 • V
REF
– 1LSB –0.5 • V
REF
– 1LSB 0 0 1 1 1 1 16383
0 ≤ –V
REF
0 0 0 0 0 0 0
The LTC2473 (differential input) output code is given by
INT(32767.5 • (V
IN
+
– V
IN
–
)/V
REF
+ 32767.5. The first bit
output by the LTC2473, D15, is the MSB, which is 1 for
V
IN
+
≥ V
IN
–
and 0 for V
IN
+
< V
IN
–
. This bit is followed by
successively less significant bits (D14, D13, …) until the
LSB is output by the LTC2473, see Table 1.
The LTC2471 (single-ended input) output code is a direct
binary encoded result, see Table 1.
LTC2471/LTC2473
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Figure 7. Timing Diagram for Writing to the LTC2471/LTC2473
Data Input Format
After a START condition, the master sends a 7-bit ad
-
dress followed by a read/write request (R/W) bit. The
R/W bit is 0 for a write. The data input word is 4 bits long
and consists of two enable bits (EN1 and EN2) and two
programming bits (SPD and SLP), see Figure 7. EN1 is
applied to the first rising edge of SCL after a valid write
address is acknowledged. Programming is enabled by
setting EN1 = 1 and EN2 = 0.
The speed bit (SPD) determines the output rate, SPD = 0
(default) for a 208sps and SPD = 1 for a 833sps output
rate. The sleep bit (SLP) is used to power down the
on-chip reference. In the default mode, the reference re-
mains powered up at the conclusion of each conversion
cycle while the ADC is automatically powered down at the
end of each conversion cycle. If the SLP bit is set HIGH,
the reference and the ADC are powered down once the next
conversion cycle is completed. The reference and ADC are
powered up again once a valid read/write is acknowledged.
The following conversion is invalid if the next conversion
is started before the reference has started up (see Figure 3
for reference startup times as a function of compensation
capacitor and reference capacitor).
The sleep bit (SLP) is used to power down the on chip
reference. In the default mode, the reference remains
powered up even when the ADC is powered down. If the
SLP bit is set HIGH, the reference will power down after
the next conversion is complete. It will remain powered
down until a valid address is acknowledged. The reference
startup time is approximately 12ms. In order to ensure a
stable reference for the following conversions, either the
data input/output time should be delayed 12ms after an
address acknowledge or the first conversion following a
reference start up should be discarded.
Table 2. Input Data Format
BIT NAME FUNCTION
EN1 Should Be High (EN1 = 1) in Order to Enable Program Mode
EN2 Should Be Low (EN2 = 0) in Order to Enable Program Mode
SPD Low (SPD = 0, Default) for 208sps, High (SPD = 1) for
833sps Output Rate
SLP Low (SLP = 0, Default) for Nap Mode, High (SLP = 1)
for Sleep Mode Where Both Reference and Converter Are
Powered Down
SDA
SCL
EN1 EN2 SPD SLP
W
SLEEP
START BY
MASTER
DATA INPUT
7 8 9
1 2 3 4 5 6 7 8 9
1 2 …
7-BIT ADDRESS
ACK BY
LTC2471/LTC2473
ACK BY
LTC2471/LTC2473
24713 F07
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

LTC2471IMS#TRPBF

Mfr. #:
Buy LTC2471IMS#TRPBF
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC Selectable 208Hz/833Hz, Single-Ended, 16-Bit delta sigma ADC with 10ppm/deg C Max Reference and I2C Interface
Lifecycle:
New from this manufacturer.
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