LTC2471/LTC2473
14
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For more information www.linear.com/LTC2471
applicaTions inForMaTion
PRESERVING THE CONVERTER ACCURACY
The LTC2471/LTC2473 are designed to minimize the conver
-
sion result’s sensitivity to device decoupling, PCB layout,
anti-aliasing circuits, line and frequency perturbations.
Nevertheless, in order to preserve the high accuracy capa-
bility of this part, some simple precautions are desirable.
Digital Signal Levels
Due to the nature of CMOS logic, it is advisable to keep input
digital signals near GND or V
CC
. Voltages in the range of
0.5V to V
CC
– 0.5V may result in additional current leakage
from the part. Undershoot and overshoot should also be
minimized, particularly while the chip is converting. It is
thus beneficial to keep edge rates of about 10ns and limit
overshoot and undershoot to less than 0.3V.
Driving V
CC
and GND
In relation to the V
CC
and GND pins, the LTC2471/LTC2473
combines internal high frequency decoupling with damping
elements, which reduce the ADC performance sensitivity
to PCB layout and external components. Nevertheless,
the very high accuracy of this converter is best pre
-
served by careful low and high frequency power supply
decoupling.
A 0.1µF, high quality, ceramic capacitor in parallel with
a 10µF low ESR ceramic capacitor should be connected
between the V
CC
and GND pins, as close as possible to the
package. The 0.1µF capacitor should be placed closest to
the ADC package. It is also desirable to avoid any via in the
circuit path, starting from the converter V
CC
pin, passing
through these two decoupling capacitors, and returning
to the converter GND pin. The area encompassed by this
circuit path, as well as the path length, should be minimized.
As shown in Figure 11, REF
–
is used as the negative
reference voltage input to the ADC. This pin can be tied
directly to ground or Kelvin sensed to sensor ground. In
the case where REF
–
is used as a sense input, it should
be bypassed to ground with a 0.1μF ceramic capacitor in
parallel with a 10μF low ESR ceramic capacitor.
Very low impedance ground and power planes, and star
connections at both V
CC
and GND pins, are preferable. The
V
CC
pin should have two distinct connections: the first to
the decoupling capacitors described above, and the second
to the ground return for the power supply voltage source.
REFOUT and COMP
The on chip 1.25V reference is internally tied to the con
-
verter’s reference input and is output to the REFOUT pin.
A 0.1μF capacitor should be placed on the REFOUT pin.
It is possible to reduce this capacitor, but the transition
noise increases (see Figure 4). A 0.1μF capacitor should
also be placed on the COMP pin. This pin is tied to an
internal point in the reference and is used for stability.
In order for the reference to remain stable, the capacitor
placed on the COMP pin must be greater than or equal
to the capacitor tied to the REFOUT pin. The REFOUT pin
cannot be overridden by an external voltage.
Depending on the size of the capacitors tied to the REFOUT
and COMP pins, the internal reference has a corresponding
start up time. This start up time is typically 12ms when
0.1μF capacitors are used. The first conversion following
power up can be discarded using the data abort com
-
Figure 11. LTC2471/LTC2473 Analog Input/Reference
Equivalent Circuit
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V
CC
V
CC
V
CC
V
CC
C
EQ
0.35pF
(TYP)
IN
+
(LTC2473)
IN
–
(LTC2473)
IN
(LTC2471)
REF
–
REFOUT
INTERNAL
REFERENCE
24713 F11
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R
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