SiC645
www.vishay.com
Vishay Siliconix
S16-2233-Rev. B, 31-Oct-16
13
Document Number: 65424
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
PCB LAYOUT FOR MINIMIZING CURRENT LOOPS
Fig. 16 - Single-Phase PCB Layout for Minimizing Current Loops
Fig. 17 - Multi-Phase PCB Layout Example Top Layer
1
2
3
5
24
LGCTRL
V
CC
+5 V PV
CC
GND
NC
GND
GND
DN
IMON
REF
IN
GND
PWM
V
IN
FAULT#
BOOT
PHASE
TMON
4
V
IN
V
IN
V
IN
GND(33)
ND
D
GN
ND
D
Inductor
SW
SW
SW
SW
SW
SW
SW
SW
9 10 11 12 13 14 15 16
8
6
7
21
22
23
27
GND
GND
GND
17
20
19
18
GND (35)
V
IN
(34)
GND
25 24262829303132
SiC645
www.vishay.com
Vishay Siliconix
S16-2233-Rev. B, 31-Oct-16
14
Document Number: 65424
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Fig. 18 - Multi-Phase PCB Layout Example Bottom Layer
PACKAGE OUTLINE DRAWING Dual cooled PowerPAK MLP55-32L
V
IN
decoupling
capacitors
Keep out area
Side view
Top view
Detail "X"
Bottom view
Pin 1 index area
D
2X
0.10
CA
A
B
E
Q1
Q2
P2
P1
See detail “X”
A
A1
A2
0.08 C
C
(Nd4-1) x e
ref.
D2-2
0.2
D2-1
0.2
32
A
M
0.10 C B
4
1
b
E2-1
E2-2
K1
K2
(Nd1-1) x e
ref.
8
(Nd2-1) x e
ref.
9
16
D2-3
L
L1
L
(Nd3) x e
ref.
e
E2-3
23
L
24
17
9
0.2 ref.
0.00 min.
0.05 max.
C
Typical recommended land pattern
(4.80)
(4.00)
(0.40)
(2.00)
(1.50)
(2 x 1.15)
(0.40)
(1.85)
(0.70)
(27 x 0.50)
(3 x 3.50)
(4.80)
(3.00)
(32 x 0.25)
(22 x 0.60)
Pin 1 index area
5
5
SiC645
www.vishay.com
Vishay Siliconix
S16-2233-Rev. B, 31-Oct-16
15
Document Number: 65424
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Notes
(1)
Use millimeters as the primary measurement.
(2)
Dimensioning and tolerances conform to ASME Y14.5M-1994.
(3)
N is the number of terminals. Nd1 and Nd3 is the number of terminals in Y-direction and Nd2 and Nd4 is the number of terminals in
X-direction.
(4)
Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal trip.
(5)
The configuration of the pin #1 identifier is optimal, but must be located within the zone indicated. The pin #1 identifier may be either a mold
or mark feature.
(6)
Exact shape and size of this feature is optional.
(7)
Package warpage max 0.08 mm.
(8)
Applied only for terminals.
(9)
Tiebar shown (if present) is a non-functional feature.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?65424
.
DIM.
MILLIMETERS
MIN. NOM. MAX.
A
(8)
0.56 0.61 0.66
A1 0.00 - 0.05
A2 0.20 ref.
b
(4)
0.20 0.25 0.30
D 5.00 BSC
D2-1 1.45 1.50 1.55
D2-2 1.95 2.00 2.05
D2-3 4.25 4.30 4.35
e 0.50 BSC
E 5.00 BSC
E2-1 1.10 1.15 1.20
E2-2 1.80 1.85 1.90
E2-3 1.10 1.15 1.20
K1 0.55 BSC
K2 0.15 BSC
L 0.35 0.40 0.45
L1 0.25 0.30 0.35
P1 3.95 4.00 4.05
P2 0.75 - 1.15
Q1 2.05 2.10 2.15
Q2 1.30 1.35 1.40
N
(3)
32
Nd1
(3)
8 (pin 1 to pin 8)
Nd2
(3)
8 (pin 9 to pin 16)
Nd3
(3)
7 (pin 17 to pin 23)
Nd4
(3)
9 (pin 24 to pin 32)

SIC645ER-T1-GE3

Mfr. #:
Manufacturer:
Vishay / Siliconix
Description:
Gate Drivers Smrt Pwr Stage VRPwr 4.5 to 18V; 5V PWM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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