SiC645
www.vishay.com
Vishay Siliconix
S16-2233-Rev. B, 31-Oct-16
7
Document Number: 65424
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
ELECTRICAL SPECIFICATIONS
(recommended operating conditions, unless otherwise noted. T
J
= -40 °C to +125 °C)
PARAMETER SYMBOL TEST CONDITIONS
LIMITS
UNIT
MIN.
a
TYP. MAX.
a
POWER RATING
Maximum instant power dissipation T
A
= 25 °C, 150 A
b
-100-
W
Maximum continuous power dissipation T
A
= 25 °C,
JA
= 10 °C/W, T
J
= 150 °C
b
- 12.5 -
THERMAL RESISTANCE
Thermal resistance junction to PCB
JB
b
-5.2-
°C/W
Thermal resistance junction to ambient
JA
0 LFM
b
- 10.7 -
400 LFM
b
-9.3-
V
CC
SUPPLY CURRENT
Logic standby current IV
CC
PWM = open - 4.75 - mA
Gate drive standby current IPV
CC
PWM = open - 100 - µA
Logic operational current IV
CC
PWM = 300 kHz - 4.75 -
mA
Gate drive operational current IPV
CC
PWM = 300 kHz - 15 -
POWER-ON RESET AND ENABLE
V
CC
rising POR threshold - 3.86 4.20
c
V
V
CC
falling POR threshold 3.20
c
3.58 -
V
CC
POR hysteresis -280-mV
V
CC
POR delay to operation - 125 197
c
µs
V
IN
rising POR threshold - 4 4.2
c
V
V
IN
falling POR threshold 3.4
c
3.5 -
V
IN
POR hysteresis -445-mV
3.3 V PWM INPUT (see “Timing Diagram”)
Sink impedance - 33.5 -
k
Source impedance - 16.5 -
Tri-state lower gate falling threshold
V
CC
= 5 V
-1.11-
V
Tri-state lower gate rising threshold - 0.87 -
Tri-state upper gate rising threshold - 2.13 -
Tri-state upper gate falling threshold - 1.95 -
Tri-state shutdown window 1.3
c
-1.8
c
5 V PWM INPUT (see “Timing Diagram”)
Sink impedance - 16.5 -
k
Source impedance - 16.5 -
Tri-state lower gate falling threshold
V
CC
= 5 V
-1.51-
V
Tri-state lower gate rising threshold - 1.14 -
Tri-state upper gate rising threshold - 3.24 -
Tri-state upper gate falling threshold - 3.02 -
Tri-state shutdown window 1.6
c
-2.8
c
SWITCHING TIME
GH turn-on propagation delay t
PDHU
GL low to GH high, see Fig. 6 - 8 -
ns
GH turn-off propagation delay t
PDLU
PWM low to GH low, see Fig. 6 - 40 -
GL turn-on propagation delay t
PDHL
GH low to GL high, see Fig. 6 - 8 -
GL turn-off propagation delay t
PDLL
PWM high to GL low, see Fig. 6 - 23 -
GL exit tri-state propagation delay t
PDTSL
Tri-state to GL high), see Fig. 6 - 25 -
GH exit tri-state propagation delay t
PDTSU
Tri-state to GH high, see Fig. 6 - 35 -
PWML tri-state shutdown hold-off time t
TSSHDL
PWM low to GL low, see Fig. 6 - 40 -
PWMH tri-state shutdown hold-off time t
TSSHDU
PWM low to GH low, see Fig. 6 - 50 -
