NCP1601AP Datasheet NCP1601BDR2G, NCP1601ADR2, NCP1601APG | P13-P15

NCP1601A, NCP1601B

http://onsemi.com

voltage is higher based on the regulation block

characteristic in Figure 31. On the other hand, the V

control

in the low V

condition is much higher than the high V

condition. In order to not over--design the circuit in the

application, the V

control

in the low V

condition is usually

very closed to V

control(max)

. It makes the output voltage be

almost 96% of the nominal value of R

 I

ref

in low V

condition while the output voltage is almost 100% of the

nominal value R

 I

ref

in high V

condition.

The feedback resistor R

consists of two or thre e high

precision resistors in orde r to set the nominal V

out

precisely

and safety purpose.

The regulation block output V

reg

is connected to control

voltage V

control

through an internal resistor R

control

(300 kΩ typical) for the low--pass filter in Figure 30. The

control

and the time information of zero current are

collected in the V

control

processing circuit to generate V

ton

which is then compared to a ramp signal to generate the

MOSFET on time t

for power factor correction.

Overvoltage Protection (OVP)

When the feedback current I

is higher than 107% of the

refere nce current I

ref

(i.e., the output voltage V

out

is higher

than 107% of i ts nomi nal value), the Drive Output pin

(Pin 7) of the device goes low for protection and the switch

of the V

control

processing circuit is kept off. The circuit

automatically resumes opera tion when the output voltage

is lower than 107%.

The maximum OVP threshold is limited to 225 mAwhich

corresponds to 225 mA  1.95 MΩ + 5 V = 443.75 V when

=1.95MΩ (1.8 MΩ + 150 kΩ) and V

FB1

= 5 V (for

the worst case referring to Figure 11). Hence, it is genera lly

recom mended to use 450 V rating output capacitor to allow

some design margin.

Undervoltage Protection (UVP)

When the feedback current I

is lower than 8% of the

refere nce current I

ref

(i.e., the output voltage V

out

is lower

than 8% of its nominal value), the device is shut down and

consumes lower than 50 mA. In normal situation of boost

convert er configura tion, the output voltage V

out

is always

higher than t he input volta ge V

and the feedback current

is always higher than 8% of the reference current I

ref

It enable s the NCP1601 to operate. Hence, UVP happens

when the output voltage is abnormally undervoltage, the

FB pin (Pin 1) is opened, or the FB pi n (Pin 1) is manually

pulled low.

Current Sense

The device senses the inductor current I

by the current

sense scheme in Figure 32. This scheme has the advantages

of: (1) the inrush current limitation by the resistor R

,and

(2) the overcurrent protection and zero current detection

implemented in the same pin.

Figure 32. Current Sensing

NCP1601

Gnd

Inductor current I

passes through R

and creates a

negative voltage. This voltage is measured by a current I

flowing out of the CS pin (Pin 4). The CS pin has an offset

voltage V

. This offset voltage is studied in the setting of

zero inductor current I

L(ZCD)

and t he maxim um inductor

current I

L(OCP)

(i.e., overcurrent protection threshold). A

typical variation of offset voltage V

versus sense current

is shown in Figure 15. Higher the value of the offset

voltage at low current region creates lower the zero c urrent

threshold for better accuracy. Based on Figure 32, (eq.13)

is derived.

(eq.13)

− R

= -- R

Zero Current Detection (ZCD)

The device recognizes zero inductor current when the CS

pin (Pin 4) sense current I

is lower than I

S(ZCD)

(14 mA

typical). The offset voltage of the CS pin in this condition

is V

S(ZCD)

(7.5 mV typical). It is illustrated in Figure 33.

The inductor current I

L(ZCD)

at the ZCD condition is

derived in (eq.14).

(eq.14)

L(ZCD)

S(ZCD)

− V

S(ZCD)

It is obvious that the I

L(ZCD)

is not always zero. In order

to make it reasonably close to zero, the settings of R

and

are crucial.

Figure 33. CS Pin Characteristic when I

S(ZCD)

Operating ZCD point

Ideal ZCD point

NCP1601A, NCP1601B

http://onsemi.com

Based on the CS pin (Pin 4) characteristics in Figure 15,

Figure 33 is studied. When the inductor current is exactly

zero (i.e., I

L(ZCD)

= 0), t he ideal ZCD point in the Figure is

reached where R

is R

S(ZCD)

(536 Ω typical). Consider ing

the tolerance, the actual sense resistor R

is needed to be

higher than the ideal value of R

S(ZCD)

to ensure that zero

current signal is generated when sense current is smaller

than the ZCD threshold (i.e., I

S(ZCD)

). That is,

> R

S(ZCD)

(eq.15)

The higher value of R

make s the longer distance

betwee n the opera ting and ideal ZCD points in Figure 33.

Hence, R

has to be as low as possible. The best

recom mended value of R

is therefore the maximum of

S(ZCD)

which is 1 kΩ.

Now that the R

is set at a particular value which is

greater than R

S(ZCD)

. From (eq.13), the operating lines in

(eq.16) with different inductor currents I

of (eq.13) are

studied.

= R

− R

(eq.16)

These operating lines are added in Figure 33 to formulate

Figure 34. When the inductor current I

is lower than

L(ZCD)

, the sense current I

is lower than I

S(ZCD)

and hence

the zero current signal is generated.

Figure 34. CS Pin Characteristic with Different

Inductor Current

S(ZCD)

Operating

ZCD point

Best

ZCD

point

L(ZCD)

It i s noted in Figure 34 and (eq.16) that when the (R

)

term is smaller the error or distance between the lines to the

line I

= 0 is smaller. Therefore, the value of the current

sense resistor R

is also recommended to be as small as

possible to minimize the error in the zero current detection.

Overcurrent Protection (OCP)

Overcurrent protection is reached when I

is higher than

S(OCP)

(200 mA typic al). The offset voltage of the CS pin

is V

S(OCP)

(3.2 mV typical) in this condition. That is

(eq.17)

L(OCP)

S(OCP)

− V

S(OCP)

When overcurrent protection threshold is reached, the

Drive Output of t he device goes low.

Oscillator / Synchronization Block

Figure 35. Oscillator / Synchronization Block

Oscillator Clock

Zero Current

Turn on

MOSFET

5 V/3.5 V

Osc

delay

45 mA

94 mA

Figure 36. Oscillator Block Timing Diagram

time

clock

inductor

clock latch

(latch set signal)

Discontinuous mode

Critical mode

(latch output)

current

clock edge

The NCP1601 is a DCM / CRM PFC controller. In order

to keep the operation in DCM or CRM only, the Drive

Output cannot turn on as long as there is some inductor

current flowing through the ci rcuit. Henc e, the zero current

signal is provided to the oscillator / synchronization block

in Figure 35. An input comparator monitors the Osc pin

(Pin 5) voltage and generates a clock signal. The negative

edge of the cloc k signal is stored in a RS latch. When zero

current is detected, the RS latc h will be reset and a set signal

is sent to the output drive latch which turns on the MOSFET

in the PFC boost circuit. Figure 36 illustrates a typical

timing diagram of the oscillator block.

Oscillator Mode

The Osc pin (Pin 5) is connected to an external capacitor

osc

. When the volta ge of this pin is above V

sync(H)

(5 V

typical), the pin sinks a current I

odch

(94 – 45 = 49 mA

typical) and the external capacitor C

osc

discharges. When

the voltage reaches V

sync (L)

(3.5 V typical), the pin sources

a current I

och

(45 mA typical) and the external capacitor

osc

is charged. It is noted that there is a typical 300 ns

propagat ion delay and the 3.5 V and 5 V threshold

conditions are measured on 220 pF C

osc

capacitor. Hence,

the actual oscillator hystere sis is a slightly smaller.

Figure 37. Oscillator Mode Timing Diagram in DCM

Osc pin

voltage

Osc c lock

Clock edge

Drive output

(DCM)

3.5 V

NCP1601A, NCP1601B

http://onsemi.com

There is an internal capacitance C

osc(int)

(36 pF typical)

in the oscillator pin and the oscillator frequency is to

osc(max)

(405 kHz typical) when the Osc pin is opened.

Hence, the oscillator switching frequency can be

formulated in (eq.18) and represented in Figure 38.

(eq.18)

osc

36 pF ⋅ 405 kHz

osc

− 36 pF

100

200

300

400

500

600

700

0 50 100 150 200

osc

, Oscillator Frequency (kHz)

osc

, Oscillator Capacitor (pF)

Figure 38. Osc Pin Frequency Setting

Synchronization Mode

The Osc pin (Pin 5) receives an external digital signal

with level high defined to be higher than V

sync(H)

(5 V

typical) and level low defined to be lower than V

sync(L)

(3.5 V typical). An internal 9 V ESD Zener diode is

connec ted to the Osc pin and hence the maximum

synchroniza tion voltage is 9 V. The circuit recognizes a

synchronization frequency by the time difference between

two falling edge instants when the synchronization signal

across the 3.5 V threshold points. The actual

synchroniza tion t hreshold point is a slightly higher than the

3.5 V threshold poi nt. The minimum synchronization pulse

width is 500 ns.

There is a typical 350 ns propagation delay from

synchronization threshold point to the moment of output goes

high and there is also a typical 300 ns propagation delay from

the synchronization threshold point to the moment of crossing

3.5 V. Hence, the output goes high apparently when the sync

sign al turns to 3.5 V. A timing diagram of sy nch ro n ization

mode is summarized in Figur e 39.

Figure 39. Synchronization Mode Timing Diagram in

DCM

Sync Signal

Osc Clock

Clock Edge

Drive Output

(DCM)

3.5 V

Undervoltage Lockout (UVLO)

There are two UVLO options. The device typi cally starts

to operate when the supply voltage V

exceeds 13.75 V

for NCP1601A and 10.5 V for NCP1601B. It turns off when

the supply voltage V

goes below 9 V. An 18 V internal

ESD Zener diode is connected to the V

pin (Pin 8).

Hence, the operating range is 9 V to 18 V.

The 4.75 V UVLO hysteresis option of the NCP1601A

and 14 mA low startup current make the self--supply design

easie r. The 1.5 V UVLO hysteresis option of NCP1601B

make s it more flexible to match with the second--stage

PWM controller biasing V

supply voltage.

Thermal Shutdown

An internal thermal circuitry disables the circuit gate

drive and then keeps the power switch off when the junction

temperature exceeds 140C. T he output stage is then

enabl ed once the temperature drops below typically 95C

(i.e., 45C hysteresis). The thermal shutdown is provided

to prevent possible device fa ilures that could result from an

accidental overheating.

Output Drive

The output stage of the device is designed for direct drive

of power MOSFET. It is capable of up to --500 mA and

+750 mA peak drive current and has a typical rise and fall

time of 53 and 32 ns with a 1.0 nF load.

Table 1. Power Factor Controller Test Data

(V ac) P

(W) V

out

(V) I

out

(mA) PF THD (%) Efficiency (%)

90 143.4 327 400 0.998 4 91.2

110 161.1 373 400 0.997 6 92.6

130 160.5 378 400 0.996 6 94.2

150 160.9 382 400 0.993 7 95.0

180 161.6 386 400 0.990 6 95.5

190 161.7 387 400 0.986 8 95.7

210 162.0 389 400 0.980 8 96.0

230 162.2 391 400 0.973 9 96.4

250 162.8 393 400 0.959 16 96.6

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P19

NCP1601AP

Mfr. #:

Buy NCP1601AP

Manufacturer:

ON Semiconductor

Description:

IC CTRLR PFC FREQ DCM/CRM 8DIP

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

NCP1601AP

NCP1601AP

Products related to this Datasheet