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AD9826KRSZ
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
AD9826
–9–
t
AD
t
AD
t
C2ADR
ANALOG
INPUTS
CDSCLK1
CDSCLK2
ADCCLK
OUTPUT
DA
T
A
D<7:0>
PIXEL n
PIXEL (n+1)
PIXEL (n+2)
t
C1
t
C2C1
t
C2
t
C2ADF
t
ADC2
t
ADCLK
t
ADCLK
HIGH
BYTE
LO
W
BYTE
CH1(n–2)
t
C1C2
CH2(n–2)
CH1(n–1)
CH2(n–1)
LO
W
BYTE
LO
W
BYTE
LO
W
BYTE
LO
W
BYTE
HIGH
BYTE
HIGH
BYTE
HIGH
BYTE
HIGH
BYTE
t
PRA
CH1(n)
Figure 3.
2-Channel CDS Mode Timing
t
AD
t
ADCLK
t
ADCLK
t
C2ADR
ANALOG
INPUTS
CDSCLK2
ADCCLK
OUTPUT
DA
T
A
D<7:0>
PIXEL n
PIXEL
(n+1)
t
C2
t
C2ADF
t
ADC2
HIGH
BYTE
LO
W
BYTE
LO
W
BYTE
LO
W
BYTE
LO
W
BYTE
LO
W
BYTE
HIGH
BYTE
HIGH
BYTE
HIGH
BYTE
HIGH
BYTE
CH1(n–2)
CH2(n–2)
CH1(n–1)
CH2(n–1)
CH1(n)
Figure 4.
2-Channel SHA Mode Timing
REV. B
AD9826
–10–
t
AD
PIXEL n (R,G,B)
t
C2
t
ADCLK
t
ADCLK
t
C2ADR
ANALOG
INPUTS
CDSCLK2
ADCCLK
OUTPUT
DA
T
A
D<7:0>
R (n–1)
t
C2AD
t
ADC2
HIGH
BYTE
LO
W
BYTE
t
OD
t
PRA
HB
LB
HB
HB
HB
HB
HB
LB
LB
LB
LB
LB
R (n–2)
G (n–2)
G (n–2)
B (n–2)
B (n–2)
R (n–1)
G (n–1)
G (n–1)
B (n–1)
B (n–1)
R (n)
R (n)
G (n)
G (n)
PIXEL (n+1)
Figure 5.
3-Channel SHA Mode Timing
HIGH BYTE
LO
W BYTE
LO
W BYTE
LO
W BYTE
HIGH BYTE
HIGH BYTE
ANALOG
INPUTS
CDSCLK2
ADCCLK
OUTPUT
DA
T
A
D<7:0>
PIXEL n
t
AD
t
C2ADR
t
OD
t
PRB
PIXEL (n–4)
PIXEL (n–4)
PIXEL (n–3)
PIXEL (n–3)
PIXEL (n–2)
PIXEL (n–2)
t
C2ADF
t
ADCLK
t
C2
t
ADCLK
t
ADCLK
NO
TE
IN 1-CHANNEL SHA MODE,
THE CDSCLK2 RISING EDGE MUST OCCUR
WHILE ADCCLK IS “LOW
.”
Figure 6.
1-Channel SHA Mode Timing
REV. B
AD9826
–11–
ADCCLK
OEB
OUTPUT
DA
T
A
<D7:D0>
HIGH BYTE
DB15–DB8
LO
W BYTE
DB7–DB0
HB
n+1
LB
n+1
LB
n+2
HB
n+3
t
DV
t
HZ
t
OD
PIXEL n
PIXEL n
t
OD
Figure 7.
Digital Output Data Timing
ADCCLK
OEB
OUTPUT
DA
T
A
<D7:D0>
HIGH BYTE
DB15–DB8
HB
n+2
HB
n+3
t
DV
t
HZ
t
OD
PIXEL n
PIXEL n+1
HIGH BYTE
DB15–DB8
Figure 8.
Single Byte Mode Digital Output Data Timing
t
LH
D8
D7
D6
D5
D4
D3
D2
D1
D0
t
DS
t
LS
t
DH
A0
A2
R/Wb
SD
A
T
A
A1
SCLK
SLO
AD
Figure 9.
Serial Write Operation Timing
t
LH
D8
D7
D6
D5
D4
D3
D2
D1
D0
t
RD
V
t
LS
A0
A2
A1
R/Wb
SD
A
T
A
SCLK
SLO
AD
Figure 10.
Serial Read Operation Timing
REV. B
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
AD9826KRSZ
Mfr. #:
Buy AD9826KRSZ
Manufacturer:
Analog Devices Inc.
Description:
Analog Front End - AFE 16-Bit Imaging Signal Processor
Lifecycle:
New from this manufacturer.
Delivery:
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Payment:
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