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AD9826KRSZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
–3–
AD9826
DIGITAL SPECIFICATIONS
Parameter Symbol Min Typ Max Unit
LOGIC INPUTS
High Level Input Voltage V
IH
2.0 V
Low Level Input Voltage V
IL
0.8 V
High Level Input Current I
IH
10 μA
Low Level Input Current I
IL
10 μA
Input Capacitance C
IN
10 pF
LOGIC OUTPUTS
High Level Output Voltage V
OH
4.5 V
Low Level Output Voltage V
OL
0.1 V
High Level Output Current I
OH
50 μA
Low Level Output Current I
OL
50 μA
LOGIC OUTPUTS (with DRVDD = 3 V)
High Level Output Voltage, (I
OH
= 50 μA) V
OH
2.95 V
Low Level Output Voltage (I
OL
= 50 μA) V
OL
0.05 V
Specifications subject to change without notice.
TIMING SPECIFICATIONS
Parameter Symbol Min Typ Max Unit
CLOCK PARAMETERS
3-Channel Pixel Rate t
PRA
200 ns
1-Channel Pixel Rate t
PRB
80 ns
ADCCLK Pulsewidth t
ADCLK
30 ns
CDSCLK1 Pulsewidth t
C1
8ns
CDSCLK2 Pulsewidth t
C2
8ns
CDSCLK1 Falling to CDSCLK2 Rising t
C1C2
0ns
ADCCLK Falling to CDSCLK2 Rising t
ADC2
0ns
CDSCLK2 Rising to ADCCLK Rising t
C2ADR
5ns
CDSCLK2 Falling to ADCCLK Falling t
C2ADF
30 ns
CDSCLK2 Falling to CDSCLK1 Rising t
C2C1
5ns
Aperture Delay for CDS Clocks t
AD
2ns
SERIAL INTERFACE
Maximum SCLK Frequency f
SCLK
10 MHz
SLOAD to SCLK Set-Up Time t
LS
10 ns
SCLK to SLOAD Hold Time t
LH
10 ns
SDATA to SCLK Rising Set-Up Time t
DS
10 ns
SCLK Rising to SDATA Hold Time t
DH
10 ns
SCLK Falling to SDATA Valid t
RDV
10 ns
DATA OUTPUTS
Output Delay t
OD
6ns
3-State to Data Valid t
DV
10 ns
Output Enable High to 3-State t
HZ
10 ns
Latency (Pipeline Delay) 3 (Fixed) Cycles
NOTES
It is recommended that CDSCLK falling edges do not occur within the first 10 ns following an ADCCLK edge.
Specifications subject to change without notice.
(T
MIN
to T
MAX
, AVDD = 5 V, DRVDD = 5 V, CDS Mode, f
ADCCLK
= 15 MHz, f
CDSCLK1
= f
CDSCLK2
= 5 MHz,
C
L
= 10 pF, unless otherwise noted.)
(T
MIN
to T
MAX
, AVDD = 5 V, DRVDD = 5 V, specs are for 16-bit performance.)
REV. B
AD9826
–4–
THERMAL CHARACTERISTICS
Thermal Resistance
28-Lead 5.3 mm SSOP
θ
JA
= 109°C/W
θ
JC
= 39°C/W
ABSOLUTE MAXIMUM RATINGS*
With
Respect
Parameter To Min Max Unit
VIN, CAPT, CAPB AVSS –0.3 AVDD + 0.3 V
Digital Inputs AVSS –0.3 AVDD + 0.3 V
AVDD AVSS –0.5 +6.5 V
DRVDD DRVSS –0.5 +6.5 V
AVSS DRVSS –0.3 +0.3 V
Digital Outputs DRVSS –0.3 DRVDD + 0.3 V
Junction Temperature 150 °C
Storage Temperature –65 +150 °C
Lead Temperature 300 °C
(10 sec)
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9826 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recom-
mended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
AD9826
–5–
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Type Description
1 CDSCLK1 DI CDS Reference Level Sampling Clock
2 CDSCLK2 DI CDS Data Level Sampling Clock
3 ADCCLK DI A/D Converter Sampling Clock
4 OEB DI Output Enable, Active Low
5 DRVDD P Digital Output Driver Supply
6 DRVSS P Digital Output Driver Ground
7 D7 DO Data Output MSB. ADC DB15 High Byte, ADC DB7 Low Byte
8 D6 DO Data Output. ADC DB14 High Byte, ADC DB6 Low Byte
9 D5 DO Data Output. ADC DB13 High Byte, ADC DB5 Low Byte
10 D4 DO Data Output. ADC DB12 High Byte, ADC DB4 Low Byte
11 D3 DO Data Output. ADC DB11 High Byte, ADC DB3 Low Byte
12 D2 DO Data Output. ADC DB10 High Byte, ADC DB2 Low Byte
13 D1 DO Data Output. ADC DB9 High Byte, ADC DB1 Low Byte
14 D0 DO Data Output LSB. ADC DB8 High Byte, ADC DB0 Low Byte
15 SDATA DI/DO Serial Interface Data Input/Output
16 SCLK DI Serial Interface Clock Input
17 SLOAD DI Serial Interface Load Pulse
18, 28 AVDD P 5 V Analog Supply
19, 27 AVSS P Analog Ground
20 CAPB AO ADC Bottom Reference Voltage Decoupling
21 CAPT AO ADC Top Reference Voltage Decoupling
22 VINB AI Analog Input, Blue Channel
23 CML AO Internal Bias Level Decoupling
24 VING AI Analog Input, Green Channel
25 OFFSET AO Clamp Bias Level Decoupling
26 VINR AI Analog Input, Red Channel
TYPE: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.
PIN CONFIGURATION
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD9826
CDSCLK1
AVDD
CDSCLK2
AVSS
VINR
ADCCLK
OFFSET
OEB
VING
DRVDD
DRVSS
CML
(MSB) D7
VINB
D6
CAPT
D5
CAPB
D4
AVSS
D3
AVDD
SLOAD
D2
SCLK
D1
(LSB) D0
SDATA
REV. B
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

AD9826KRSZ

Mfr. #:
Buy AD9826KRSZ
Manufacturer:
Analog Devices Inc.
Description:
Analog Front End - AFE 16-Bit Imaging Signal Processor
Lifecycle:
New from this manufacturer.
Delivery:
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