CS5530-ISZ Datasheet CS5530-ISZ, CS5530-ISZR | P25-P27

CS5530

DS742F3 25

2.6 Using Multiple ADCs Synchronously

Some applications require synchronous data out-

puts from multiple ADCs converting different ana-

log channels. Multiple CS5530 devices can be

synchronized in a single system by using the fol-

lowing guidelines:

1) All of the ADCs in the system must be operated

from the same oscillator source.

2) All of the ADCs in the system must share com-

mon SCLK and SDI lines.

3) A software reset must be performed at the same

time for all of the ADCs after system power-up (by

selecting all of the ADCs using their respective CS

pins, and writing the reset sequence to all parts, us-

ing SDI and SCLK).

4) A start conversion command must be sent to all

of the ADCs in the system at the same time. The ±

8 clock cycles of ambiguity for the first conversion

(or for a single conversion) will be the same for all

ADCs, provided that they were all reset at the same

time.

5) Conversions can be obtained by monitoring

SDO on only one ADC, (bring CS high for all but

one part) and reading the data out of each part indi-

vidually, before the next conversion data words are

ready.

An example of a synchronous system using two

CS5530 devices is shown in Figure 12.

2.7 Conversion Output Coding

The CS5530 outputs 24-bit data conversion words.

To read a conversion word the user must read the

conversion data register. The conversion data reg-

ister is 32 bits long and outputs the conversions

MSB first. The last byte of the conversion data reg-

ister contains an overflow flag bit. The overrange

flag (OF) monitors to determine if a valid conver-

sion was performed.

The CS5530 output data conversions in binary for-

mat when operating in unipolar mode and in two's

complement when operating in bipolar mode. Ta-

ble 3 shows the code mapping for both unipolar and

bipolar modes. VFS in the tables refers to the posi-

tive full-scale voltage range of the converter in the

specified gain range, and -VFS refers to the nega-

tive full-scale voltage range of the converter. The

total differential input range (between AIN+ and

AIN-) is from 0 to VFS in unipolar mode, and from

-VFS to VFS in bipolar mode.

CLOCK

SOURCE

CS5530

SDO

SDI

SCLK

OSC2

SDO

SDI

SCLK

OSC2

μC

Figure 12. Synchronizing Multiple ADCs

Table 3. Output Coding

Unipolar Input

Voltage

Offset

Binary

Bipolar Input

Voltage

Two's

Complement

>(VFS-1.5 LSB) FFFFFF >(VFS-1.5 LSB) 7FFFFF

VFS-1.5 LSB FFFFFF

------

FFFFFE

VFS-1.5 LSB

7FFFFF

------

7FFFFE

VFS/2-0.5 LSB 800000

------

7FFFFF

-0.5 LSB

000000

------

FFFFFF

+0.5 LSB 000001

------

000000

-VFS+0.5 LSB

800001

------

800000

<(+0.5 LSB) 000000 <(-VFS+0.5 LSB) 800000

CS5530

26 DS742F3

2.7.1 Conversion Data Output Descriptions

CS5530 (24-BIT CONVERSIONS)

Conversion Data Bits [31:8]

These bits depict the latest output conversion.

OF (Over-range Flag Bit) [2]

0 Bit is clear when over-range condition has not occurred.

1 Bit is set when input signal is more positive than the positive full-scale, more negative than zero (unipolar

mode) or when the input is more negative than the negative full-scale (bipolar mode).

Other Bits [7:3], [1:0]

These bits are masked logic zero.

D31(MSB) D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

MSB 2221201918 1716151413121110 9 8

D15 D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

7 65432 1LSB00000OF00

CS5530

DS742F3 27

2.8 Digital Filter

The CS5530 has a linear phase digital filter which

is programmed to achieve a range of output word

rates (OWRs) as stated in the Configuration Regis-

ter Description section. The ADC uses a Sinc

dig-

ital filter to output word rates at 3200 Sps and 3840

Sps (MCLK = 4.9152 MHz). Other output word

rates are achieved by using the Sinc

filter followed

by a Sinc

filter with a programmable decimation

rate.Figure 13 shows the magnitude response of the

60 Sps filter, while Figures 14 and 15 show the

magnitude and phase response of the filter at 120

Sps. The Sinc

is active for all output word rates

except for the 3200 Sps and 3840 Sps (MCLK =

4.9152 MHz) rate. The Z-transforms of the two fil-

ters are shown in Figure 16. For the Sinc

filter,

“D” is the programmable decimation ratio, which is

equal to 3840/OWR when FRS = 0 and 3200/OWR

when FRS = 1.

The converter’s digital filters scale with MCLK.

For example, with an output word rate of 120 Sps,

the filter’s corner frequency is at 31 Hz. If MCLK

is increased to 5.0 MHz, the OWR increases by

1.0175 percent and the filter’s corner frequency

moves to 31.54 Hz. Note that the converter is not

specified to run at MCLK clock frequencies greater

than 5 MHz.

Figure 13. Digital Filter Response (Word Rate = 60 Sps)

-120

-80

-40

Gain (dB)

0 60 120 180 240 300

Frequency (Hz)

FRS = 0

-120

-80

-40

04080120

Frequency (Hz)

Gain (dB)

Flatness

Frequency dB

2-0.01

4-0.05

6-0.11

8-0.19

10 -0.30

12 -0.43

14 -0.59

16 -0.77

19 -1.09

32 -3.13

Figure 14. 120 Sps Filter Magnitude Plot to 120 Hz

-180

-90

180

60 90 120

Frequency (Hz)

Phase (Degrees)

Figure 15. 120 Sps Filter Phase Plot to 120 Hz

Note: See the text regarding the Sinc

filter’s

decimation ratio “D”.

Sinc

1 z

80–

–()

1 z

16–

–()

--------------------------

1 z

16–

–()

1 z

4–

–()

--------------------------

1 z

4–

–()

1 z

2–

–()

-----------------------

1 z

2–

–()

1 z

1–

–()

-----------------------

×××=

Sinc

1 z

D–

–()

1 z

1–

–()

-------------------------=

Figure 16. Z-Transforms of Digital Filters

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36

CS5530-ISZ

Mfr. #:

Buy CS5530-ISZ

Manufacturer:

Cirrus Logic

Description:

Analog to Digital Converters - ADC 24-Bit 1-Ch Low Noise ADC

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CS5530-ISZ

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