© Semiconductor Components Industries, LLC, 2015
January, 2015 − Rev. 8
1 Publication Order Number:
MC74AC74/D
MC74AC74, MC74ACT74
Dual D-Type Positive
Edge-Triggered Flip-Flop
The MC74AC74/74ACT74 is a dual D−type flip−flop with
Asynchronous Clear and Set inputs and complementary (Q,Q
)
outputs. Information at the input is transferred to the outputs on the
positive edge of the clock pulse. Clock triggering occurs at a voltage
level of the clock pulse and is not directly related to the transition time
of the positive-going pulse. After the Clock Pulse input threshold
voltage has been passed, the Data input is locked out and information
present will not be transferred to the outputs until the next rising edge
of the Clock Pulse input.
Asynchronous Inputs:
LOW input to S
D
(Set) sets Q to HIGH level
LOW input to C
D
(Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C
D
and S
D
makes both Q and Q HIGH
Features
Outputs Source/Sink 24 mA
ACT74 Has TTL Compatible Inputs
These are Pb−Free Devices
CP
1
C
D
2
CP
2
1314 12 11 10 9 8
21 34567
V
CC
C
D1
D
1
CP
1
S
D1
Q
1
Q
1
C
D2
D
2
CP
2
S
D2
Q
2
Q
2
C
D
1
S
D
1
Q
1
D
1
S
D
2
Q
2
Q
2
D
2
GND
Q
1
Figure 1. Pinout: 14−Lead Packages Conductors
(Top View)
PIN ASSIGNMENT
PIN FUNCTION
D
1
, D
2
Data Inputs
CP
1
, CP
2
Clock Pulse Inputs
C
D1
, C
D2
Direct Clear Inputs
S
D1
, S
D2
Direct Set Inputs
Q
1
, Q
1
, Q
2
,
Q
2
Outputs
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
ORDERING INFORMATION
www.onsemi.com
MARKING
DIAGRAMS
xxx = AC or ACT
A = Assembly Location
WL or L = Wafer Lot
Y = Year
WW or W = Work Week
G or G = Pb−Free Package
TSSOP−14
DT SUFFIX
CASE 948G
xxx
74
ALYWG
G
1
14
SOIC−14
D SUFFIX
CASE 751A
1
14
1
14
xxx74G
AWLYWW
1
14
(Note: Microdot may be in either location)
MC74AC74, MC74ACT74
www.onsemi.com
2
TRUTH TABLE (Each Half)
Inputs Outputs
S
D
C
D
CP D Q Q
L H X X H L
H L X X L H
L L X X H H
H H H H L
H H L L H
H H L X Q
0
Q
0
NOTE: H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial;
= LOW-to-HIGH Clock Transition
Q
0
(Q
0
) = Previous Q(Q) before LOW-to-HIGH
Transition of Clock
Figure 2. Logic Symbol
S
D1
Q
1
CP
1
Q
1
C
D1
S
D2
Q
2
D
2
CP
2
Q
2
CD
2
D
1
S
D
D
CP
C
D
Q
Q
Figure 3. Logic Diagram
NOTE: This diagram is provided only for the understanding of
logic operations and should not be used to estimate
propagation delays.
MC74AC74, MC74ACT74
www.onsemi.com
3
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage *0.5 to )7.0 V
V
I
DC Input Voltage *0.5 v V
I
v V
CC
)0.5 V
V
O
DC Output Voltage (Note 1) *0.5 v V
O
v V
CC
)0.5 V
I
IK
DC Input Diode Current $20 mA
I
OK
DC Output Diode Current $50 mA
I
O
DC Output Sink/Source Current $50 mA
I
CC
DC Supply Current per Output Pin $50 mA
I
GND
DC Ground Current per Output Pin $50 mA
T
STG
Storage Temperature Range *65 to )150 °C
T
L
Lead temperature, 1 mm from Case for 10 Seconds 260 °C
T
J
Junction temperature under Bias )150 °C
q
JA
Thermal Resistance (Note 2) SOIC
TSSOP
125
170
°C/W
P
D
Power Dissipation in Still Air at 85°C SOIC
TSSOP
125
170
mW
MSL Moisture Sensitivity Level 1
F
R
Flammability Rating Oxygen Index: 30% − 35% UL 94 V−0 @ 0.125 in
V
ESD
ESD Withstand Voltage Human Body Model (Note 3)
Machine Model (Note 4)
Charged Device Model (Note 5)
> 2000
> 200
> 1000
V
I
Latch−Up
Latch−Up Performance Above V
CC
and Below GND at 85°C (Note 6) $100 mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. I
O
absolute maximum rating must be observed.
2. The package thermal impedance is calculated in accordance with JESD51−7.
3. Tested to EIA/JESD22−A114−A.
4. Tested to EIA/JESD22−A115−A.
5. Tested to JESD22−C101−A.
6. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Typ Max Unit
V
CC
Supply Voltage
AC 2.0 5.0 6.0
V
ACT 4.5 5.0 5.5
V
in
, V
out
DC Input Voltage, Output Voltage (Ref. to GND) 0 V
CC
V
t
r
, t
f
Input Rise and Fall Time (Note )
AC Devices except Schmitt Inputs
V
CC
@ 3.0 V 150
V
CC
@ 4.5 V 40 ns/V
V
CC
@ 5.5 V 25
t
r
, t
f
Input Rise and Fall Time (Note )
ACT Devices except Schmitt Inputs
V
CC
@ 4.5 V 10
ns/V
V
CC
@ 5.5 V 8.0
T
J
Junction Temperature (PDIP) 140 °C
T
A
Operating Ambient Temperature Range −40 25 85 °C
I
OH
Output Current − High −24 mA
I
OL
Output Current − Low 24 mA
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
1. V
in
from 30% to 70% V
CC
; see individual Data Sheets for devices that differ from the typical input rise and fall times.
2. V
in
from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.

MC74AC74NG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
IC FF D-TYPE DUAL 1BIT 14DIP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union