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ADF4208BRUZ-R7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
Dual RF PLL Frequency Synthesizers
ADF4206/ADF4208
Rev. A
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
FEATURES
ADF4206: 550 MHz/550 MHz
ADF4208: 2.0 GHz/1.1 GHz
2.7 V to 5.5 V power supply
Selectable charge pump supply (V
P
) allows extended
tuning voltage in 3 V systems
Selectable charge pump currents
On-chip oscillator circuit
Selectable dual modulus prescaler
RF2: 32/33 or 64/65
RF1: 32/33 or 64/65
3-wire serial interface
Power-down mode
APPLICATIONS
Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA)
Base stations for wireless radio (GSM, PCS, DCS,
CDMA, WCDMA)
Wireless LANS
Communications test equipment
CATV equipment
GENERAL DESCRIPTION
The ADF420x family of dual frequency synthesizers are used
to implement local oscillators in the upconversion and down-
conversion sections of wireless receivers and transmitters. Each
synthesizer consists of a low noise, digital, phase frequency detector
(PFD); a precision charge pump; a programmable reference
divider; programmable A and B counters; and a dual modulus
prescaler (P/P + 1). The A (6-bit) and B (11-bit) counters, in
conjunction with the dual modulus prescaler (P/P + 1), implement
an N divider (N = BP + A). In addition, the 14-bit reference
counter (R counter) allows selectable REFIN frequencies at the
PFD input. The on-chip oscillator circuitry allows the reference
input to be derived from crystal oscillators.
A complete phase-locked loop (PLL) can be implemented if the
synthesizers are used with an external loop filter and voltage
controlled oscillators (VCOs).
Control of all the on-chip registers is via a simple 3-wire
interface. The devices operate with a power supply ranging
from 2.7 V to 5.5 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
OSCILLATOR
CLK
DATA
LE
22-BIT
DATA
REGISTER
MUXOUT
ADF4206/ADF4208
CP
RF1
CP
RF2
PHASE
COMPARATOR
OUTPUT
MUX
14-BIT RF2
R-COUNTER
OSC
IN
RF1
IN
A
RF1
IN
B
V
DD
1
V
DD
2
V
P
1
V
P
2
AGND
RF1
DGND
RF1
DGND
RF2
AGND
RF2
SDOUT
RF2
PRESCALER
RF2
IN
A
11-BIT RF2
B-COUNTER
6-BIT RF2
A-COUNTER
RF2
IN
B
OSC
OUT
N=BP+A
CHARGE
PUMP
RF2
LOCK
DETECT
14-BIT RF1
R-COUNTER
RF1
PRESCALER
11-BIT RF1
B-COUNTER
6-BIT RF1
A-COUNTER
N=BP+A
RF1
LOCK
DETECT
PHASE
COMPARATOR
CHARGE
PUMP
01036-001
Figure 1.
ADF4206/ADF4208
Rev. A | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 5
Timing Diagram ........................................................................... 5
Absolute Maximum Ratings............................................................ 6
Transistor Count........................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Circuit Description......................................................................... 11
Reference Input Section............................................................. 11
RF Input Stage............................................................................. 11
Prescaler....................................................................................... 11
A and B Counters ....................................................................... 11
Pulse Swallow Function............................................................. 11
R Counter .................................................................................... 11
Phase Frequency Detector (PFD) and Charge Pump............ 12
MUXOUT and Lock Detect...................................................... 12
Lock Detect ................................................................................. 12
Input Shift Register .................................................................... 12
Program Modes .............................................................................. 18
Power-Down ............................................................................... 18
IF Section (RF2) ......................................................................... 18
RF Section (RF1) ........................................................................ 19
Applications Section....................................................................... 20
Local Oscillator for GSM Handset Receiver........................... 20
Local Oscillator for WCDMA Receiver .................................. 21
Interfacing ....................................................................................... 22
ADuC812 Interface .................................................................... 22
ADSP-2181 Interface ................................................................. 22
Outline Dimensions ....................................................................... 23
Ordering Guide .......................................................................... 24
REVISION HISTORY
2/06—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Deleted ADF4207 ...............................................................Universal
Changes to Table 3............................................................................ 6
Changes to Function Description .................................................. 7
Changes to Table 4............................................................................ 7
Changes to Figure 22 Caption....................................................... 12
Changes to Pulse Swallow Function ............................................ 13
Changes to Figure 29...................................................................... 15
Changes to Figure 31...................................................................... 17
Updated Outline Dimensions....................................................... 25
Changes to Ordering Guide .......................................................... 25
3/01—Revision 0: Initial Version
ADF4206/ADF4208
Rev. A | Page 3 of 24
SPECIFICATIONS
V
DD
1 = V
DD
2 = 3 V ± 10%, 5 V ± 10%; V
DD
1, V
DD
2 ≤ V
P
1, V
P
2 ≤ 6.0 V; AGND
RF1
= DGND
RF1
= AGND
RF2
= DGND
RF2
= 0 V;
T
A
= T
MIN
to T
MAX
, unless otherwise noted; dBm referred to 50 Ω.
Table 1.
Parameter B Version
1
B Chips
2
Unit Test Conditions/Comments
RF/IF CHARACTERISTICS (3 V) See Figure 22 for input circuit
RF1 Input Frequency (RF1
IN
)
ADF4206 0.05/0.55 0.05/0.55 GHz min/max For f < 50 MHz ensure SR > 23 V/µs
ADF4208 0.08/2.0 0.08/2.0 GHz min/max For f < 50 MHz ensure SR > 37 V/µs
RF Input Sensitivity –15/+4 −15/+4 dBm min/max
IF Input Frequency (RF2
IN
)
ADF4206 0.05/0.55 0.05/0.55 GHz min/max For f < 50 MHz ensure SR > 23 V/µs
ADF4208 0.08/1.1 0.08/1.1 GHz min/max For f < 50 MHz ensure SR > 37 V/µs
IF Input Sensitivity −15/+4 −15/+4 dBm min/max
Maximum Allowable Prescaler 165 165 MHz max
Output Frequency
3
RF CHARACTERISTICS (5 V)
RF1 Input Frequency (RF1
IN
)
ADF4206 0.05/0.55 0.05/0.55 GHz min/max For f < 50 MHz ensure SR > 32 V/µs
ADF4208 0.08/2.0 0.08/2.0 GHz min/max For f < 50 MHz ensure SR > 51 V/µs
RF Input Sensitivity −10/+4 −10/+4 dBm min/max
IF Input Frequency (RF2
IN
) MHz min/max
ADF4206 0.05/0.55 0.05/0.55 GHz min/max For f < 50 MHz ensure SR > 32 V/µs
ADF4208 0.08/1.1 0.08/1.1 GHz min/max For f < 50 MHz ensure SR > 51 V/µs
IF Input Sensitivity −10/+4 –10/+4 dBm min/max
Maximum Allowable Prescaler 200 200 MHz max
Output Frequency
3
REFIN CHARACTERISTICS
REFIN Input Frequency 5/40 5/40 MHz min/max For f < 5 MHz ensure SR > 9 V/µs
REFIN Input Sensitivity
4
−2 −2 dBm min
REFIN Input Capacitance 10 10 pF max
REFIN Input Current ±100 ±100 A max
PHASE DETECTOR
Phase Detector Frequency
5
55 55 MHz max
CHARGE PUMP
I
CP
Sink/Source
High Value 5 5 mA typ
Low Value 1.25 1.25 mA typ
Absolute Accuracy 2.5 2.5 % typ
I
CP
Three-State Leakage Current 1 1 nA typ
LOGIC INPUTS
V
INH
, Input High Voltage 0.8 × V
DD
0.8 × V
DD
V min
V
INL
, Input Low Voltage 0.2 × V
DD
0.2 × V
DD
V max
I
INH
/I
INL
, Input Current ±1 ±1 A max
C
IN
, Input Capacitance 10 10 pF max
LOGIC OUTPUTS
V
OH
, Output High Voltage V
DD
− 0.4 V
DD
− 0.4 V min I
OH
= 500 A
V
OL
, Output Low Voltage 0.4 0.4 V max I
OL
= 500 A
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

ADF4208BRUZ-R7

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Buy ADF4208BRUZ-R7
Manufacturer:
Analog Devices Inc.
Description:
Phase Locked Loops - PLL Dual Integer-N 1.1 GHz/2.0 GHz
Lifecycle:
New from this manufacturer.
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