ADF4206/ADF4208
Rev. A | Page 7 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V
DD
1
V
P
1
CP
RF1
DGND
RF1
RF1
IN
OSC
IN
OSC
OUT
MUXOUT
V
DD
2
V
P
2
CP
RF2
DGND
RF2
RF2
IN
LE
DATA
CLK
01036-003
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ADF4206
TOP VIEW
(Not to Scale)
V
DD
1
CP
RF1
DGND
RF1
RF1
IN
A
OSC
IN
OSC
OUT
MUXOUT
RF1
IN
B
AGND
RF1
V
DD
2
CP
RF2
AGND
RF2
LE
DATA
CLK
RF2
IN
B
RF2
IN
A
DGND
RF2
01036-004
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
ADF4208
TOP VIEW
(Not to Scale)
V
P
1
V
P
2
Figure 3. 16-Lead TSSOP Pin Configuration Figure 4. 20-Lead TSSOP Pin Configuration
Table 4. Pin Function Descriptions
ADF4206
Pin No.
ADF4208
Pin No.
Mnemonic Description
1 1 V
DD
1
Positive Power Supply for the RF1 Section. A 0.1 F capacitor is connected between this pin
and DGND
RF1
(the RF1 ground pin). V
DD
1 should have a value of between 2.7 V and 5.5 V. V
DD
1
must have the same potential as V
DD
2.
2 2 V
P
1 Power Supply for the RF1 Charge Pump. This is greater than or equal to V
DD
.
3 3 CP
RF1
Output from the RF1 Charge Pump. This is normally connected to a loop filter that drives the
input to an external VCO.
4 4 DGND
RF1
Ground Pin for the RF1 Digital Circuitry.
5 5 RF1
IN
/RF1
IN
A Input to the RF1 Prescaler. This low level input signal is taken from the RF1 VCO.
6 8 OSC
IN
Oscillator Input. It has a V
DD
/2 threshold and is driven from an external CMOS or TTL logic gate.
7 9 OSC
OUT
Oscillator Output.
8 10 MUXOUT
This multiplexer output allows the IF/RF lock detect, the scaled RF, or the scaled reference
frequency external access. See
Figure 30.
9 11 CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is
latched into the 22-bit shift register on the CLK rising edge. This input is a high impedance
CMOS input.
10 12 DATA
Serial Data Input. The serial data is loaded MSB first with the two LSBs as the control bits. This
input is a high impedance CMOS input.
11 13 LE
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded
into one of the four latches, the latch being selected using the control bits.
12 16 RF2
IN
/RF2
IN
A
Input to the RF2 Prescaler. This low level input signal is normally ac-coupled to the external
VCO.
13 17 DGND
RF2
Ground Pin for the RF2, Digital, Interface, and Control Circuitry.
14 18 CP
RF2
Output from the RF2 Charge Pump. This is normally connected to a loop filter that drives the
input to an external VCO.
15 19 V
P
2 Power Supply for the RF2 Charge Pump. This is greater than or equal to V
DD
.
16 20 V
DD
2
Positive Power Supply for the RF2, Interface, and Oscillator Sections. A 0.1 F capacitor is
connected between this pin and DGND
RF2
(the RF2 ground pin). V
DD
2 has a value between 2.7 V
and 5.5 V. V
DD
2 must have the same potential as V
DD
1.
N/A 6 RF1
IN
B
Complementary Input to the RF1 Prescaler of the ADF4208. This point is decoupled to the
ground plane with a small bypass capacitor.
N/A 7 AGND
RF1
Ground Pin for the RF1 Analog Circuitry.
N/A 14 AGND
RF2
Ground Pin for the RF2 Analog Circuitry.
N/A 15 RF2
IN
B
Complementary Input to the RF2 Prescaler. This point is decoupled to the ground plane with a
small bypass capacitor.
