Data Sheet AD7790
Rev. A | Page 15 of 20
Single Conversion Mode
In single conversion mode, the AD7790 is placed in shutdown
mode between conversions. When a single conversion is initiat-
ed by setting MD1 to 1 and MD0 to 0 in the mode register, the
AD7790 powers up, performs a single conversion, and then
returns to shutdown mode. A conversion will require a time
period of 2 × t
ADC
. DOUT/
RDY
goes low to indicate the com-
pletion of a conversion. When the data-word has been read
from the data register, DOUT/
RDY
will go high. If
CS
is low,
DOUT/
RDY
will remain high until another conversion is initi-
ated and completed. The data register can be read several times,
if required, even when DOUT/
RDY
has gone high.
Continuous Conversion Mode
This is the default power-up mode. The AD7790 will continu-
ously convert, the
RDY
pin in the status register going low each
time a conversion is complete. If
CS
is low, the DOUT/
RDY
line
will also go low when a conversion is complete. To read a con-
version, the user can write to the communications register,
indicating that the next operation is a read of the data register.
The digital conversion will be placed on the DOUT/
RDY
pin as
soon as SCLK pulses are applied to the ADC. DOUT/
RDY
will
return high when the conversion is read. The user can read this
register additional times, if required. However, the user must
ensure that the data register is not being accessed at the comple-
tion of the next conversion or else the new conversion word will
be lost.
03538-0-011
DIN
SCLK
DOUT/RDY
CS
0x10 0x380x82
DATA
Figure 8. Single Conversion
03538-0-012
DIN
SCLK
DOUT/RDY
CS
0x38 0x38
DATA DATA
Figure 9. Continuous Conversion
AD7790 Data Sheet
Rev. A | Page 16 of 20
Continuous Read Mode
Rather than write to the communications register each time a
conversion is complete to access the data, the AD7790 can be
placed in continuous read mode. By writing 001111XX to the
communications register, the user only needs to apply the
appropriate number of SCLK cycles to the ADC and the 16-bit
word will automatically be placed on the DOUT/
RDY
line
when a conversion is complete.
When DOUT/
RDY
goes low to indicate the end of a conver-
sion, sufficient SCLK cycles must be applied to the ADC and
the data conversion will be placed on the DOUT/
RDY
line.
When the conversion is read, DOUT/
RDY
will return high
until the next conversion is available. In this mode, the data can
be read only once. Also, the user must ensure that the data-
word is read
before the next conversion is complete. If the user has not read
the conversion before the completion of the next conversion or
if insufficient serial clocks are applied to the AD7790 to read
the word, the serial output register is reset when the next con-
version is complete and the new conversion is placed in the
output serial register.
To exit the continuous read mode, the instruction 001110XX
must be written to the communications register while the
RDY
pin is low. While in the continuous read mode, the ADC
monitors activity on the DIN line so that it can receive the
instruction to exit the continuous read mode. Additionally, a
reset will occur if 32 consecutive 1s are seen on DIN. Therefore,
DIN should be held low in continuous read mode until an
instruction is to be written to the device.
03538-0-011
DIN
SCLK
DOUT/RDY
CS
0x3C
DATA DATA DATA
Figure 10. Continuous Read
Data Sheet AD7790
Rev. A | Page 17 of 20
CIRCUIT DESCRIPTION
ANALOG INPUT CHANNEL
The AD7790 has one differential analog input channel. This is
connected to the on-chip buffer amplifier when the device is
operated in buffered mode and directly to the modulator when
the device is operated in unbuffered mode. In buffered mode
(the BUF bit in the mode register is set to 1), the input channel
feeds into a high impedance input stage of the buffer amplifier.
Therefore, the input can tolerate significant source impedances
and is tailored for direct connection to external resistive-type
sensors such as strain gauges or resistance temperature detec-
tors (RTDs).
When BUF = 0, the part is operated in unbuffered mode.
This results in a higher analog input current. Note that this
unbuffered input path provides a dynamic load to the driving
source. Therefore, resistor/capacitor combinations on the
input pins can cause dc gain errors, depending on the output
impedance of the source that is driving the ADC input. Table 16
shows the allowable external resistance/capacitance values for
unbuffered mode such that no gain error at the 16-bit level is
introduced.
Table 16. External R-C Combination for No 16-Bit Gain Error
C (pF) R (Ω)
50 22.8K
100 13.1K
500 3.3K
1000 1.8K
5000 360
The absolute input voltage range in buffered mode is restricted
to a range between GND + 100 mV and V
DD
– 100 mV. Care
must be taken in setting up the common-mode voltage so that
these limits are not exceeded. Otherwise, there will be degrada-
tion in linearity and noise performance.
The absolute input voltage in unbuffered mode includes the
range between GND – 30 mV and V
DD
+ 30 mV as a result of
being unbuffered. The negative absolute input voltage limit does
allow the possibility of monitoring small true bipolar signals
with respect to GND.
PROGRAMMABLE GAIN AMPLIFIER
The output from the buffer on the ADC is applied to the input
of the on-chip programmable gain amplifier (PGA). The PGA
gain range is programmed via the gain bits G1 and G0 in the
mode register. With an external 2.5 V reference applied, the
PGA can be programmed to have a bipolar range of ±2.5 V,
±1.25 V, ±625 mV, or ±312.5 mV. These are the ranges that
should appear at the input to the on-chip PGA.
BIPOLAR CONFIGURATION
The analog input to the AD7790 accepts a bipolar input voltage
range. A bipolar input range does not imply that the part can
tolerate negative voltages with respect to system GND. Bipolar
signals on the AIN(+) input are referenced to the voltage on the
AIN(–) input. For example, if AIN(–) is 2.5 V and the ADC is
configured for a gain of 1, the analog input range on the AIN(+)
input is 0 V to 5 V.
DATA OUTPUT CODING
The output code is offset binary with a negative full-scale volt-
age resulting in a code of 000...000, a zero differential input
voltage resulting in a code of 100...000, and a positive full-scale
input voltage resulting in a code of 111...111. The output code
for any analog input voltage can be represented as
Code = 2
N – 1
× [(AIN × GAIN/V
REF
) + 1]
where AIN is the analog input voltage, GAIN is the PGA gain,
and N = 16.
REFERENCE INPUT
The AD7790 has a fully differential input capability for the
channel. The common-mode range for these differential inputs
is from GND to V
DD
. The reference input is unbuffered and,
therefore, excessive R-C source impedances will introduce gain
errors. The reference voltage REFIN (REFIN(+) – REFIN(–)) is
2.5 V nominal for specified operation, but the AD7790 is func-
tional with reference voltages from 0.1 V to V
DD
. In applications
where the excitation (voltage or current) for the transducer on
the analog input also drives the reference voltage for the part,
the effect of the low frequency noise in the excitation source
will be removed because the application is ratiometric. If the
AD7790 is used in a nonratiometric application, a low noise
reference should be used.
Recommended 2.5 V reference voltage sources for the AD7790
include the ADR381 and ADR391 because these are low noise,
low power references. If the complete analog section is driven
from a 2.5 V power supply, the reference voltage source will
require some headroom. In this case, a 2.048 V reference such
as the ADR380 is recommended, again low noise, low power
references. Also note that the reference inputs provide a high
impedance, dynamic load. Because the input impedance of each
reference input is dynamic, resistor/capacitor combinations on
these inputs can cause dc gain errors, depending on the output
impedance of the source that is driving the reference inputs.
Reference voltage sources like those recommended above (e.g.,
ADR391) will typically have low output impedances and are,
therefore, tolerant to having decoupling capacitors on

AD7790BRMZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 16-Bit SGL-Ch Ultra Low Power
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