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AD7790BRMZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
Data Sheet AD7790
Rev. A | Page 3 of 20
AD7790—SPECIFICATIONS
1
Table 1. (V
DD
= 2.5 V to 5.25 V; REFIN(+) = 2.5 V; REFIN(–) = GND; CDIV1 = CDIV0 = 0; GND = 0 V;
all specifications T
MIN
to T
MAX
, unless otherwise noted.)
Parameter AD7790B Unit Test Conditions/Comments
ADC CHANNEL SPECIFICATION
Output Update Rate 9.5 Hz min nom
120 Hz max nom
ADC CHANNEL
No Missing Codes
2
16 Bits min
±V
REF
Range, Update Rate
≤
20 Hz
Resolution 16 Bits p-p 9.5 Hz Update Rate
Output Noise 1.1 µV rms typ
Integral Nonlinearity ±15 ppm of FSR max 3.5 ppm typ
Offset Error ±3 µV typ
Offset Error Drift vs. Temperature ±10 nV/°C typ
Full-Scale Error
3
±10 µV typ
Gain Drift vs. Temperature ±0.5 ppm/°C typ
Power Supply Rejection 90 dB min Input Range = ±REFIN, 100 dB typ
ANALOG INPUTS
Differential Input Voltage Ranges ±REFIN/GAIN V nom REFIN = REFIN(+) – REFIN(–); GAIN = 1, 2, 4, or 8
Absolute AIN Voltage Limits
2
GND + 100 mV V min Buffered Mode of Operation
V
DD
– 100 mV V max
Analog Input Current Buffered Mode of Operation
Average Input Current
2
±1
nA max
Average Input Current Drift ±5 pA/°C typ
Absolute AIN Voltage Limits
2
GND – 30 mV V min Unbuffered Mode of Operation
V
DD
+ 30 mV V max
Analog Input Current
Unbuffered Mode of Operation
Input current varies with input voltage.
Average Input Current ±400 nA/V typ
Average Input Current Drift ±50 pA/V/°C typ
Normal Mode Rejection
2
@ 50 Hz, 60 Hz 65 dB min 73 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[2:0] = 100
4
@ 50 Hz 80 dB min 90 dB typ, 50 ± 1 Hz, FS[2:0] = 101
4
@ 60 Hz
80
dB min
90 dB typ, 60 ± 1 Hz, FS[2:0] = 011
4
Common Mode Rejection Input Range = ±REFIN, AIN = 1 V
@ DC 90 dB min 100 dB typ (FS[2:0] = 100
4
)
@ 50 Hz, 60 Hz
2
100 dB min 50 ± 1 Hz (FS[2:0] = 101
4
), 60 ± 1 Hz (FS[2:0] = 011
4
)
REFERENCE INPUT REFIN = REFIN(+) – REFIN(–)
REFIN Voltage 2.5 V nom
Reference Voltage Range
2
0.1 V min
V
DD
V max
Absolute REFIN Voltage Limits
2
GND – 30 mV
V min
V
DD
+ 30 mV V max
Average Reference Input Current 0.5 µA/V typ
Average Reference Input Current Drift ±0.03 nA/V/°C typ
1
Temperature Range –40°C to +105°C.
2
Specification is not production tested, but is supported by characterization data at initial product release.
3
Full-scale error applies to both positive and negative full-scale and applies at the factory calibration conditions (V
DD
= 4 V).
4
FS[2:0] are the three bits used in the filter register to select the output word rate.
AD7790 Data Sheet
Rev. A | Page 4 of 20
SPECIFICATIONS (continued)
1
Parameter AD7790B Unit Test Conditions/Comments
REFERENCE INPUT (continued)
Normal Mode Rejection
2
@ 50 Hz, 60 Hz 65 dB min 73 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[2:0] = 100
4
@ 50 Hz 80 dB min 90 dB typ, 50 ± 1 Hz, FS[2:0] = 101
4
@ 60 Hz 80 dB min 90 dB typ, 60 ± 1 Hz, FS[2:0] = 011
4
Common Mode Rejection
Input Range = ±2.5 V, AIN = 1 V
@ DC 100 dB typ FS[2:0] = 100
4
@ 50 Hz, 60 Hz 110 dB typ 50 ± 1 Hz (FS[2:0] = 101
4
), 60 ± 1 Hz (FS[2:0] = 011
4
)
LOGIC INPUTS
All Inputs Except SCLK
2
V
INL
, Input Low Voltage 0.8 V max V
DD
= 5 V
0.4 V max V
DD
= 3 V
V
INH
, Input High Voltage 2.0 V min V
DD
= 3 V or 5 V
SCLK Only (Schmitt-Triggered Input)
2
V
T
(+) 1.4/2 V min/V max V
DD
= 5 V
V
T
(–) 0.8/1.4 V min/V max V
DD
= 5 V
V
T
(+) – V
T
(–) 0.3/0.85 V min/V max V
DD
= 5 V
V
T
(+) 0.9/2 V min/V max V
DD
= 3 V
V
T
(–) 0.4/1.1 V min/V max V
DD
= 3 V
V
T
(+) - V
T
(–)
0.3/0.85
V min/V max
V
DD
= 3 V
Input Currents ±1 µA max V
IN
= V
DD
or GND
Input Capacitance 10 pF typ All Digital Inputs
LOGIC OUTPUTS
V
OH
, Output High Voltage
2
V
DD
– 0.6 V min V
DD
= 3 V, I
SOURCE
= 100 µA
V
OL
, Output Low Voltage
2
0.4 V max V
DD
= 3 V, I
SINK
= 100 µA
V
OH
, Output High Voltage
2
4 V min V
DD
= 5 V, I
SOURCE
= 200 µA
V
OL
, Output Low Voltage
2
0.4 V max V
DD
= 5 V, I
SINK
= 1.6 mA
Floating-State Leakage Current ±1 µA max
Floating-State Output Capacitance 10 pF typ
Data Output Coding Offset Binary
POWER REQUIREMENTS
5
Power Supply Voltage
V
DD
– GND 2.5/5.25 V min/max
Power Supply Currents
I
DD
Current
6
75 µA max 65 µA typ, V
DD
= 3.6 V, Unbuffered Mode
145 µA max 130 µA typ, V
DD
= 3.6 V, Buffered Mode
80
µA max
73 µA typ, V
DD
= 5.25 V, Unbuffered Mode
160 µA max 145 µA typ, V
DD
= 5.25 V, Buffered Mode
I
DD
(Power-Down Mode) 1 µA max
5
Digital inputs equal to V
DD
or GND.
6
The current consumption can be further reduced by using the ADC in one of the low power modes (see Table 15).
Data Sheet AD7790
Rev. A | Page 5 of 20
TIMING CHARACTERISTICS
1, 2
Table 2. (V
DD
= 2.5 V to 5.25 V; GND = 0 V, REFIN(+) = 2.5 V, REFIN(–) = GND, CDIV1 = CDIV0 = 0, Input Logic 0 = 0 V,
Input Logic 1 = V
DD
, unless otherwise noted.)
Parameter
Limit at T
MIN
, T
MAX
(B Version) Unit Conditions/Comments
t
3
100 ns min SCLK High Pulsewidth
t
4
100 ns min SCLK Low Pulsewidth
Read Operation
t
1
0 ns min
CS Falling Edge to DOUT/RDY Active Time
60 ns max V
DD
= 4.75 V to 5.25 V
80 ns max V
DD
= 2.5 V to 3.6 V
t
2
3
0 ns min SCLK Active Edge to Data Valid Delay
4
60
V
DD
= 4.75 V to 5.25 V
80 ns max V
DD
= 2.5 V to 3.6 V
t
5
5, 6
10 ns min
Bus Relinquish Time after
CS Inactive Edge
80 ns max
t
6
100 ns max
SCLK Inactive Edge to
CS Inactive Edge
t
7
10 ns min
SCLK Inactive Edge to DOUT/
RDY High
Write Operation
t
8
0 ns min
CS Falling Edge to SCLK Active Edge Setup Time
4
t
9
30 ns min Data Valid to SCLK Edge Setup Time
t
10
25 ns min Data Valid to SCLK Edge Hold Time
t
11
0 ns min
CS Rising Edge to SCLK Edge Hold Time
1
Sample tested during initial release to ensure compliance. All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
2
See Figure 3 and Figure 4.
3
These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the V
OL
or V
OH
limits.
4
SCLK active edge is falling edge of SCLK.
5
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and, as such, are independent of external bus loading capacitances.
6
RDY
returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while
RDY
is high,
although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read
only once.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

AD7790BRMZ

Mfr. #:
Buy AD7790BRMZ
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 16-Bit SGL-Ch Ultra Low Power
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