74HCU04DTR2G

© Semiconductor Components Industries, LLC, 2007
March, 2007 Rev. 0
1 Publication Order Number:
74HCU04/D
74HCU04
Hex Unbuffered Inverter
HighPerformance SiliconGate CMOS
The 74HCU04 is identical in pinout to the LS04 and the
MC14069UB. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL
outputs.
This device consists of six singlestage inverters. These inverters
are well suited for use as oscillators, pulse shapers, and in many other
applications requiring a highinput impedance amplifier. For digital
applications, the HC04 is recommended.
Features
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V; 2.5 to 6.0 V in Oscillator
Configurations
Low Input Current: 1.0 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance With the JEDEC Standard No. 7.0 A Requirements
ESD Performance: HBM > 2000 V; Machine Model > 200 V
Chip Complexity: 12 FETs or 3 Equivalent Gates
These are PbFree Devices
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MARKING
DIAGRAMS
HCU04 = Specific Device Code
A = Assembly Location
L, WL = Wafer Lot
Y = Year
W, WW = Work Week
G or G = PbFree Package
TSSOP14
DT SUFFIX
CASE 948G
14
1
SOIC14
D SUFFIX
CASE 751A
14
1
HCU04G
AWLYWW
1
14
HCU
04
ALYWG
G
1
14
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
(Note: Microdot may be in either location)
74HCU04
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2
LOGIC DIAGRAM
Y1A1
A2
A3
A4
A5
A6
Y2
Y3
Y4
Y5
Y6
1
3
5
9
11
13
2
4
6
8
10
12
Y = A PIN 14 = V
CC
PIN 7 = GND
FUNCTION TABLE
Inputs
A
L
H
Outputs
Y
H
L
PIN ASSIGNMENT
11
12
13
14
8
9
105
4
3
2
1
7
6
Y5
A5
Y6
A6
V
CC
Y4
A4
Y2
A2
Y1
A1
GND
Y3
A3
ORDERING INFORMATION
Device Package Shipping
74HCU04DR2G SOIC14
(PbFree)
2500 / Tape & Reel
74HCU04DTR2G TSSOP14*
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently PbFree.
74HCU04
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3
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V
V
in
DC Input Voltage (Referenced to GND) – 0.5 to V
CC
+ 0.5 V
V
out
DC Output Voltage (Referenced to GND) – 0.5 to V
CC
+ 0.5 V
I
in
DC Input Current, per Pin ±20 mA
I
out
DC Output Current, per Pin ±25 mA
I
CC
DC Supply Current, V
CC
and GND Pins ±50 mA
P
D
Power Dissipation in Still Air SOIC Package†
TSSOP Package†
500
450
mW
T
stg
Storage Temperature – 65 to + 150
_C
T
L
Lead Temperature, 1 mm from case for 10 Seconds
SOIC or TSSOP Package
260
_C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Derating SOIC Package: –7mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage (Referenced to GND) 2.0 6.0 V
V
in
, V
out
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
CC
V
T
A
Operating Temperature, All Package Types – 55 + 125
_C
t
r
, t
f
Input Rise and Fall Time (Figure 1) No
Limit
ns
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this highimpedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND v (V
in
or V
out
) v V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.

74HCU04DTR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Inverters HEX UNBUFFED INVERTR
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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