© Semiconductor Components Industries, LLC, 2015
December, 2015 − Rev. 3
1 Publication Order Number:
CAV25M01/D
CAV25M01
1 Mb SPI Serial CMOS
EEPROM
Description
The CAV25M01 is a 1M−bit Serial CMOS EEPROM device
internally organized as 128Kx8 bits. This features a 256−byte page
write buffer and supports the Serial Peripheral Interface (SPI)
protocol. The device is enabled through a Chip Select (CS
) input. In
addition, the required bus signals are clock input (SCK), data input
(SI) and data output (SO) lines. The HOLD
input may be used to pause
any serial communication with the CAV25M01 device. The device
features software and hardware write protection, including partial as
well as full array protection.
On−Chip ECC (Error Correction Code) makes the device suitable
for high reliability applications.
Features
Automotive Temperature Grade 1 (−40°C to +125°C)
10 MHz SPI Compatible
2.5 V to 5.5 V Supply Voltage Range
SPI Modes (0,0) & (1,1)
256−byte Page Write Buffer
Additional Identification Page with Permanent Write Protection
Self−timed Write Cycle
Hardware and Software Protection
Block Write Protection –
Protect 1/4, 1/2 or Entire EEPROM Array
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
8 lead SOIC, TSSOP and WLCSP Packages
This Device is Pb−Free, Halogen Free/BFR Free and is RoHS
Compliant
Figure 1. Functional Symbol
SO
V
SS
CAV25M01
V
CC
SI
CS
WP
HOLD
SCK
This document contains information on some products that are still under development.
ON Semiconductor reserves the right to change or discontinue these products without
notice.
www.onsemi.com
See detailed ordering and shipping information in the packag
e
dimensions section on page 14 of this data sheet.
ORDERING INFORMATION
PIN CONFIGURATION
SI
HOLD
V
CC
V
SS
WP
SO
CS
1
SCK
SOIC (V),
TSSOP (Y)
(Top View)
Chip SelectCS
Serial Data OutputSO
Write ProtectWP
GroundV
SS
Serial Data InputSI
Serial ClockSCK
FunctionPin Name
PIN FUNCTION
Hold Transmission InputHOLD
Power SupplyV
CC
SOIC−8
V SUFFIX
CASE 751BD
TSSOP−8
Y SUFFIX
CASE 948AL
WLCSP8
C8A SUFFIX
CASE 567MP
WLCSP (C8A)
(Top View)
VCC
HOLD
VSS
WP
CS
SI
SO
SCK
Referenc
e
Pin A1
CAV25M01
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2
MARKING DIAGRAMS
25M01A = Specific Device Code
A = Assembly Location
Y = Production Year (Last Digit)
M = Production Month (1−9, O, N, D)
XXX = Last Three Digits of
XXX = Assembly Lot Number
25M01A
AYMXXX
(SOIC−8)
(TSSOP−8)
SM1A
AYMXXX
SM1A = Specific Device Code
A = Assembly Location
Y = Production Year (Last Digit)
M = Production Month (1−9, O, N, D)
XXX = Last Three Digits of
= Assembly Lot Number
G = Pb−Free Microdot
G
25M = Specific Device Code
A = Assembly Location
Y = Year
W = Work Week
25M
AYW
(WLCSP−8)
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter Ratings Units
Operating Temperature −45 to +130 °C
Storage Temperature −65 to +150 °C
Voltage on any Pin with Respect to Ground (Note 1) −0.5 to +6.5 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than V
CC
+ 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than −1.5 V or overshoot to no more than V
CC
+ 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol
Parameter Min Units
N
END
(Note 3) Endurance 1,000,000 Program / Erase Cycles
T
DR
Data Retention 100 Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, V
CC
= 5 V, 25°C
4. The device uses ECC (Error Correction Code) logic with 6 ECC bits to correct one bit error in 4 data bytes. Therefore, when a single byte
has to be written, 4 bytes (including the ECC bits) are re−programmed. It is recommended to write by multiple of 4 bytes in order to benefit
from the maximum number of write cycles.
Table 3. D. C. OPERATING CHARACTERISTICS (V
CC
= 2.5 V to 5.5 V, T
A
= −40°C to +125°C, unless otherwise specified)
Symbol
Parameter Test Conditions Min Max Units
I
CCR
Supply Current
(Read Mode)
Read, SO open f
SCK
= 10 MHz 3 mA
I
CCW
Supply Current
(Write Mode)
Write, CS = V
CC
3 mA
I
SB1
Standby Current V
IN
= GND or V
CC
, CS = V
CC
, WP = V
CC
,
HOLD
= V
CC
, V
CC
= 5.5 V
3
mA
I
SB2
Standby Current V
IN
= GND or V
CC
, CS = V
CC
, WP = GND,
HOLD
= GND, V
CC
= 5.5 V
5
mA
I
L
Input Leakage Current V
IN
= GND or V
CC
−2 2
mA
I
LO
Output Leakage Current CS = V
CC
, V
OUT
= GND or V
CC
−2 2
mA
V
IL
Input Low Voltage −0.5 0.3V
CC
V
V
IH
Input High Voltage 0.7V
CC
V
CC
+ 0.5 V
V
OL
Output Low Voltage I
OL
= 3.0 mA 0.4 V
V
OH
Output High Voltage I
OH
= −1.6 mA V
CC
− 0.8V V
CAV25M01
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3
Table 4. PIN CAPACITANCE (T
A
= 25°C, f = 1.0 MHz, V
CC
= +5.0 V) (Note 5)
Symbol
Test Conditions Min Typ Max Units
C
OUT
Output Capacitance (SO) V
OUT
= 0 V 8 pF
C
IN
Input Capacitance (CS, SCK, SI, WP, HOLD) V
IN
= 0 V 8 pF
5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
Table 5. A.C. CHARACTERISTICS (T
A
= −40°C to +125°C, unless otherwise specified.) (Note 6)
Symbol
Parameter Min Max Units
f
SCK
Clock Frequency DC 10 MHz
t
SU
Data Setup Time 10 ns
t
H
Data Hold Time 10 ns
t
WH
SCK High Time 40 ns
t
WL
SCK Low Time 40 ns
t
LZ
HOLD to Output Low Z 25 ns
t
RI
(Note 8) Input Rise Time 2
ms
t
FI
(Note 8) Input Fall Time 2
ms
t
HD
HOLD Setup Time 0 ns
t
CD
HOLD Hold Time 10 ns
t
V
Output Valid from Clock Low 40 ns
t
HO
Output Hold Time 0 ns
t
DIS
Output Disable Time 20 ns
t
HZ
HOLD to Output High Z 25 ns
t
CS
CS High Time 40 ns
t
CSS
CS Setup Time 30 ns
t
CSH
CS Hold Time 30 ns
t
CNS
CS Inactive Setup Time 30 ns
t
CNH
CS Inactive Hold Time 30 ns
t
WPS
WP Setup Time 10 ns
t
WPH
WP Hold Time 10 ns
t
WC
(Note 7) Write Cycle Time 5 ms
6. AC Test Conditions:
Input Pulse Voltages: 0.3 V
CC
to 0.7 V
CC
Input rise and fall times: 10 ns
Input and output reference voltages: 0.5 V
CC
Output load: current source I
OL
max
/I
OH
max
; C
L
= 30 pF
7. t
WC
is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
Table 6. POWER−UP TIMING (Notes 8 and 9)
Symbol Parameter Max Units
t
PUR
Power−up to Read Operation 1 ms
t
PUW
Power−up to Write Operation 1 ms
8. This parameter is tested initially and after a design or process change that affects the parameter.
9. t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.

CAV25M01YE-GT3

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
EEPROM 1 Mb SPI Serial CMOS EEPROM
Lifecycle:
New from this manufacturer.
Delivery:
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