CAV25M01
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7
Byte Write
Once the WEL bit is set, the user may execute a write
sequence, by sending a WRITE instruction, a 24−bit address
and a data byte as shown in Figure 5. Only 17 significant
address bits are used by the CAV25M01. The rest are don’t
care bits, as shown in Table 11. Internal programming will
start after the low to high CS
transition. During an internal
write cycle, all commands, except for RDSR (Read Status
Register) will be ignored. The RDY
bit will indicate if the
internal write cycle is in progress (RDY
high), or the device
is ready to accept commands (RDY
low).
Page Write
After sending the first data byte to the CAV25M01, the
host may continue sending data, up to a total of 256 bytes,
according to timing shown in Figure 6. After each data byte,
the lower order address bits are automatically incremented,
while the higher order address bits (page address) remain
unchanged. If during this process the end of page is
exceeded, then loading will “roll over” to the first byte in the
page, thus possibly overwriting previoualy loaded data.
Following completion of the write cycle, the CAV25M01 is
automatically returned to the write disable state.
Write Identification Page
The additional 256−byte Identification Page (IP) can be
written with user data using the same Write commands
sequence as used for Page Write to the main memory array
(Figure 6). The IPL bit from the Status Register must be set
(IPL = 1) using the WRSR instruction, before attempting
to write to the IP.
The address bits [A23:A8] are Don’t Care and the
[A7:A0] bits define the byte address within the
Identification Page. In addition, the Byte Address must point
to a location outside the protected area defined by the BP1,
BP0 bits from the Status Register. When the full memory
array is write protected (BP1, BP0 = 1,1), the write
instruction to the IP is not accepted and not executed.
Also, the write to the IP is not accepted if the LIP bit from
the Status Register is set to 1 (the page is locked in
Read−only mode).
Table 11. BYTE ADDRESS
Device Address Significant Bits Address Don’t Care Bits # Address Clock Pulses
Main Memory Array A16 − A0 A23 – A17 24
Identification Page A7 − A0 A23 – A8 24
Figure 5. Byte WRITE Timing
SCK
SI
SO
000000 10
D7 D6 D5 D4 D3 D2 D1 D0
0 1 2 3 4 5 6 7 8 2930313233343536373839
OPCODE
DATA IN
HIGH IMPEDANCE
BYTE ADDRESS*
Note: Dashed Line = mode (1, 1)
* Please check the Byte Address Table (Table 11)
CS
A
N
A
0
Figure 6. Page WRITE Timing
Note: Dashed Line = mode (1, 1)
SCK
SI
SO
000000 10
BYTE ADDRESS*
Data
Byte 1
012345678 29303132−39 40−47
Data
Byte 2
Data Byte N
OPCODE
7..1
0
32+(N−1)x8−1....32+(N−1)x8
32+Nx8−1
DATA IN
HIGH IMPEDANCE
CS
A
N
A
0
* Please check the Byte Address Table (Table 11)
