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74SSTU32864BFG8

P1-P3P4-P6P7-P9P10-P12
7
COMMERCIAL TEMPERATURE RANGE
IDT74SSTU32864/A/C/D/G
1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O
TERMINAL FUNCTIONS (ALL PINS)
Terminal Electrical
Name Characteristics Description
GND Ground Input Ground
VDD 1.8V nominal Power Supply Voltage
VREF 0.9V nominal Input Reference Voltage
ZOH
(1)
LVCMOS Output Slew Rate Control
ZOL
(1)
LVCMOS Output Slew Rate Control
CL K Differential Input Positive Master Clock Input
CLK Differential Input Negative Master Clock Input
Cx LVCMOS Input Configuration Control Inputs
RESET LVCMOS Input Asynchronous Reset Input. Resets registers and disables VREF data and clock differential-input receivers.
CSR, DCS SSTL_18 Input Chip Select Inputs. Disables outputs Dx switching when both inputs are HIGH.
D x SSTL_18 Input Data Input. Clocked in on the crossing of the rising edge of CLK and the falling edge of CLK.
DODT SSTL_18 Input The outputs of this register bit will not be suspended by the DCS and CSR controls
DCKE SSTL_18 Input The outputs of this register bit will not be suspended by the DCS and CSR controls
Q x 1.8V CMOS Data Outputs that are suspended by the DCS and CSR controls
QCSx 1.8V CMOS Data Output that will not be suspended by the DCS and CSR controls
QODTx 1.8V CMOS Data Output that will not be suspended by the DCS and CSR controls
QCKEx 1.8V CMOS Data Output that will not be suspended by the DCS and CSR controls
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Description Max. Unit
VDD Supply Voltage Range –0.5 to 2.5 V
VI
(2,3)
Input Voltage Range –0.5 to 2.5 V
VO
(2,3)
Output Voltage Range –0.5 to VDD +0.5 V
I
IK Input Clamp Current VI < 0 ±50 mA
VI > VDD
IOK Output Clamp Current VO < 0 ±50 mA
VO > VDD
IO Continuous Output Current, ±50 mA
VO = 0 to VDD
VDD Continuous Current through each ±100 mA
VDD or GND
T
STG Storage Temperature Range –65 to +150 ° C
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. The input and output negative voltage ratings may be exceeded if the ratings of the
I/P and O/P clamp current are observed.
3. This value is limited to 2.5V maximum.
NOTE:
1. The signals will be left unconnected for the SSTU32864/A/C/D.
8
COMMERCIAL TEMPERATURE RANGE
IDT74SSTU32864/A/C/D/G
1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O
OPERATING CHARACTERISTICS, TA = 25ºC
(1,2)
Symbol Parameter Min. Typ. Max. Unit
VDD Supply Voltage 1.7 — 1.9 V
VREF Reference Voltage 0.49 * VDD 0.5 * VDD 0.51 * VDD V
VTT Termination Voltage VREF– 40mV VREF VREF+ 40mV V
VI Input Voltage 0 — VDD V
VIH AC High-Level Input Voltage Data Inputs VREF+ 250mV — — V
VIL AC Low-Level Input Voltage Data Inputs — — VREF– 250mV V
VIH DC High-Level Input Voltage Data Inputs VREF+ 125mV — — V
VIL DC Low-Level Input Voltage Data Inputs — — VREF– 125mV V
VIH High-Level Input Voltage RESET, Cx 0.65 * VDD ——V
VIL Low-Level Input Voltage RESET, Cx — — 0.35 * VDD V
VICR Common Mode Input Voltage CLK, CLK 0.675 — 1.125 V
VID Differential Input Voltage CLK, CLK 600 — — mV
IOH High-Level Output Current — — –8 mA
IOL Low-Level Output Current — — 8
T
A Operating Free-Air Temperature 0 — 70 ° C
NOTES:
1. The RESET and Cx inputs of the device must be held at valid levels (not floating) to ensure proper device operation.
2. The differential inputs must not be floating unless RESET is LOW.
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VOH VDD = 1.7V to 1.9V, IOH = –6mA 1.2 — — V
VOL VDD = 1.7V to 1.9V, IOL = 6mA — — 0.5 V
II All Inputs VI = VDD or GND –5 — 5 μA
I
DD Static Standby IO = 0, VDD = 1.9V, RESET = GND — — 100 μA
Static Operating IO = 0, VDD = 1.9V, RESET = VDD, VI = VIH (AC) or VIL (AC) ——40mA
I
DDD Dynamic Operating IO = 0, VDD = 1.8V, RESET = VDD, VI = VIH (AC) or VIL (AC),———μA/Clock
(Clock Only) CLK and CLK Switching 50% Duty Cycle. MHz
IO = 0, VDD = 1.8V, RESET = VDD, 1:1 Mode — — —
Dynamic Operating V
I = VIH (AC) or VIL (AC), CLK and CLK Switching at μA/Clock
(Per Each Data Input) 50% Duty Cycle. One Data Input Switching at 1:2 Mode — — — MHz/Data
Half Clock Frequency, 50% Duty Cycle. Input
Data Inputs V
I = VREF ± 250mV 2.5 — 3.5
C
I CLK and CLK VICR = 0.9V, VID = 600mV 2 — 3 pF
RESET VI = VDD or GND 2 — 4
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = 0°C to +70°C, VDD = 1.8V ±0.1V
9
COMMERCIAL TEMPERATURE RANGE
IDT74SSTU32864/A/C/D/G
1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O
TIMING REQUIREMENTS OVER RECOMMENDED OPERATING FREE-AIR
TEMPERATURE RANGE
VDD = 1.8V ± 0.1V
Symbol Parameter Min. Max. Unit
fCLOCK
(1)
Clock Frequency — 340 MHz
tw Pulse Duration, CLK, CLK HIGH or LOW 1 — ns
tACT
(2)
Differential Inputs Active Time — 10 ns
tINACT
(3)
Differential Inputs Inactive Time — 15 ns
DCS before CLK↑, CLK↓, CSR HIGH 0.7 —
t
SU Setup Time DCS before CLK↑, CLK↓, CSR LOW 0.5 — ns
DODT, CSR, Data, and DCKE before CLK↑, CLK↓ 0.5 —
t
H Hold Time Data, DCS, CSR, DCKE, and DODT after CLK↑, CLK↓ 0.5 — ns
NOTES:
1. 270MHz max clock frequency for parts assembled and tested prior to WW37.
2. Data and VREF inputs must be low a minimum time of tACT max, after RESET is taken HIGH.
3. Data, VREF, and clock inputs must be held at valid levels (not floating) a minimum time of tINACT max, after RESET is taken LOW.
SWITCHING CHARACTERISTICS OVER RECOMMENDED FREE-AIR OPERATING
RANGE (UNLESS OTHERWISE NOTED)
(1)
VDD = 1.8V ± 0.1V
Symbol Parameter Min Max. Unit
fMAX 340 — M Hz
tPDM
(2)
CLK and CLK to Q 1.41 2.15 ns
tPDMSS
(2,3)
CLK and CLK to Q (simultaneous switching) — 2.35 ns
tRPHL RESET to Q — 3 ns
dV/dt_r Output slew rate from 20% to 80% 1 4 V/ns
dV/dt_f Output slew rate from 20% to 80% 1 4 V/ns
dV/dt_Δ
(4)
Output slew rate from 20% to 80% — 1 V/ns
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS.
2. Includes 350ps of test load transmission line delay.
3. This parameter is not production tested.
4. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate).
P1-P3P4-P6P7-P9P10-P12

74SSTU32864BFG8

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IC BUFFER 1:1/1:2 96-LFBGA
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