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AD9833SRMZ-EP-RL7

P1-P3P4-P6P7-P9P10-P12
AD9833-EP Enhanced Product
Rev. 0 | Page 4 of 12
TIMING CHARACTERISTICS
VDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, unless otherwise noted.
1
Table 2.
Parameter Limit at T
MIN
to T
MAX
Unit Description
t
1
40 ns min MCLK period
t
2
16 ns min MCLK high duration
t
3
16 ns min MCLK low duration
t
4
25 ns min SCLK period
t
5
10 ns min SCLK high duration
t
6
10 ns min SCLK low duration
t
7
5 ns min FSYNC to SCLK falling edge setup time
t
8
min
10 ns min FSYNC to SCLK hold time
t
8
max
t
4
− 5 ns max
t
9
5 ns min Data setup time
t
10
3 ns min Data hold time
t
11
5 ns min SCLK high to FSYNC falling edge setup time
1
Guaranteed by design, not production tested.
Timing Diagrams
t
2
t
1
MCLK
t
3
11545-003
Figure 3. Master Clock
t
5
t
4
t
6
t
7
t
8
t
10
t
9
D0 D14D15D1D2D14
SCLK
FSYNC
S
DAT
A
D15
t
11
11545-004
Figure 4. Serial Timing
Enhanced Product AD9833-EP
Rev. 0 | Page 5 of 12
ABSOLUTE MAXIMUM RATINGS
T
A
= 25°C, unless otherwise noted.
Table 3.
Parameter Rating
VDD to AGND −0.3 V to +6 V
VDD to DGND −0.3 V to +6 V
AGND to DGND −0.3 V to +0.3 V
CAP/2.5V 2.75 V
Digital I/O Voltage to DGND −0.3 V to VDD + 0.3 V
Analog I/O Voltage to AGND −0.3 V to VDD + 0.3 V
Operating Temperature Range
−55°C to +125°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature 150°C
MSOP Package
θ
JA
Thermal Impedance 206°C/W
θ
JC
Thermal Impedance 44°C/W
Lead Temperature, Soldering (10 sec) 300°C
IR Reflow, Peak Temperature 220°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD9833-EP Enhanced Product
Rev. 0 | Page 6 of 12
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 COMP DAC Bias Pin. This pin is used for decoupling the DAC bias voltage.
2 VDD Positive Power Supply for the Analog and Digital Interface Sections. The on-board 2.5 V regulator is also supplied
from VDD. VDD can have a value from 2.3 V to 5.5 V. A 0.1 µF and a 10 µF decoupling capacitor should be connected
between VDD and AGND.
3 CAP/2.5V The digital circuitry operates from a 2.5 V power supply. This 2.5 V is generated from VDD using an on-board
regulator when VDD exceeds 2.7 V. The regulator requires a decoupling capacitor of 100 nF typical, which is
connected from CAP/2.5V to DGND. If VDD is less than or equal to 2.7 V, CAP/2.5V should be tied directly to VDD.
4 DGND Digital Ground.
5 MCLK Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK. The
output frequency accuracy and phase noise are determined by this clock.
6 SDATA Serial Data Input. The 16-bit serial data-word is applied to this input.
7 SCLK Serial Clock Input. Data is clocked into the AD9833-EP on each falling edge of SCLK.
8 FSYNC Active Low Control Input. FSYNC
is the frame synchronization signal for the input data. When FSYNC is taken low,
the internal logic is informed that a new word is being loaded into the device.
9 AGND Analog Ground.
10 VOUT Voltage Output. The analog and digital output from the AD9833-EP is available at this pin. An external load
resistor is not required because the device has a 200 Ω resistor on board.
P1-P3P4-P6P7-P9P10-P12

AD9833SRMZ-EP-RL7

Mfr. #:
Buy AD9833SRMZ-EP-RL7
Manufacturer:
Analog Devices Inc.
Description:
Data Acquisition ADCs/DACs - Specialized 10 bit 10 pin DDS I.C.
Lifecycle:
New from this manufacturer.
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