AT17LV040A-10BJC Datasheet AT17LV002A-10QC, AT17LV002A-10CU, AT17LV512A-10JI | P4-P6

AT17LV65A/128A/256A/512A/002A

2322D–CNFG–07/02

Device Description The control signals for the configuration EEPROM (nCS, RESET/OE and DCLK) inter-

face directly with the FPGA device control signals. All FPGA devices can control the

entire configuration process and retrieve data from the configuration EEPROM without

requiring an external controller.

The configuration EEPROM’s RESET/OE

and nCS pins control the tri-state buffer on

the DATA output pin and enable the address counter and the oscillator. When

RESET/OE

is driven Low, the configuration EEPROM resets its address counter and tri-

states its DATA pin. The nCS pin also controls the output of the AT17A series configura-

tor. If nCS is held High after the RESET/OE

pulse, the counter is disabled and the DATA

output pin is tri-stated. When nCS is driven subsequently Low, the counter and the

DATA output pin are enabled. When RESET/OE

is driven Low again, the address

counter is reset and the DATA output pin is tri-stated, regardless of the state of the nCS.

When the configurator has driven out all of its data and nCASC is driven Low, the device

tri-states the DATA pin to avoid contention with other configurators. Upon power-up, the

address counter is automatically reset.

This is the default setting for the device. Since almost all FPGAs use RESET Low and

OE High, this document will describe RESET

/OE.

AT17LV65A/128A/256A/512A/002A

2322D–CNFG–07/02

DATA Three-state DATA output for configuration. Open-collector bi-directional pin for

programming.

DCLK Clock output or clock input. Rising edges on DCLK increment the internal address

counter and present the next bit of data to the DATA pin. The counter is incremented

only if the RESET/OE

input is held High, the nCS input is held Low, and all configuration

data has not been transferred to the target device (otherwise, as the master device, the

DCLK pin drives Low).

WP1 WRITE PROTECT (1). This pin is used to protect portions of memory during program-

ming, and it is disabled by default due to internal pull-down resistor. This input pin is not

used during FPGA loading operations. This pin is only available on

AT17LV512A/010A/002A devices.

RESET/OE Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low

logic level resets the address counter. A High logic level (with nCS Low) enables DATA

and permits the address counter to count. In the mode, if this pin is Low (reset), the

internal oscillator becomes inactive and DCLK drives Low. The logic polarity of this input

is programmable and must be programmed active High (RESET active Low) by the user

during programming for Altera applications.

WP Write protect (WP) input (when nCS is Low) during programming only (SER_EN Low).

When WP is Low, the entire memory can be written. When WP is enabled (High), the

lowest block of the memory cannot be written. This pin is only available on

AT17LV65A/128A/256A devices.

Pin Description

Name I/O

AT17LV65A/

AT17LV128A/

AT17LV256A

AT17LV512A/

AT17LV010A AT17LV002A

PLCC

PDIP

PLCC

TQFP

PLCC

TQFP

DATAI/O2 1 231231

DCLKI424242

WP1 I ––5454

RESET/OE

I838787

nCSI9 4 910910

GND 10 5 10121012

nCASC O

12 6 12151215

A2 I

READY O ––15 20 15 20

SER_EN

I18 7 18231823

20 8 20272027

AT17LV65A/128A/256A/512A/002A

2322D–CNFG–07/02

nCS Chip Select input (active Low). A Low input (with OE High) allows DCLK to increment

the address counter and enables DATA to drive out. If the AT17A series is reset with

nCS Low, the device initializes as the first (and master) device in a daisy-chain. If the

AT17A series is reset with nCS High, the device initializes as a subsequent AT17A

series device in the chain.

GND Ground pin. A 0.2 µF decoupling capacitor between V

and GND is recommended.

nCASC Cascade Select Output (active Low). This output goes Low when the address counter

has reached its maximum value. In a daisy-chain of AT17A series devices, the nCASC

pin of one device is usually connected to the nCS input pin of the next device in the

chain, which permits DCLK from the master configurator to clock data from a subse-

quent AT17A series device in the chain.

A2 Device selection input, A2. This is used to enable (or select) the device during program-

ming (i.e., when SER_EN

is Low). A2 has an internal pull-down resistor.

READY Open collector reset state indicator. Driven Low during power-on reset cycle, released

when power-up is complete. (recommended 4.7 kΩ pull-up on this pin if used).

SER_EN Serial enable must be held High during FPGA loading operations. Bringing SER_EN

Low enables the 2-wire Serial Programming Mode. For non-ISP applications, SER_EN

should be tied to V

3.3V (±10%) and 5.0V (±5% Commercial, ±10% Industrial) power supply pin.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P19

AT17LV040A-10BJC

Mfr. #:

Buy AT17LV040A-10BJC

Manufacturer:

Description:

IC SRL CONFG EEPROM 4M LV 44PLCC

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

AT17LV040A-10BJC

AT17LV040A-10BJC

Products related to this Datasheet