7
AT17LV65A/128A/256A/512A/002A
2322D–CNFG–07/02
FPGA Master Serial
Mode Summary
The I/O and logic functions of any SRAM-based FPGA are established by a configura-
tion program. The program is loaded either automatically upon power-up, or on
command, depending on the state of the FPGA mode pins. In Master mode, the FPGA
automatically loads the configuration program from an external memory. The AT17A
Serial Configuration EEPROM has been designed for compatibility with the Master
Serial mode.
This document discusses the Altera FLEX FPGA device interfaces
Control of
Configuration
Most connections between the FPGA device and the AT17A Serial EEPROM are simple
and self-explanatory.
• The DATA output of the AT17A series configurator drives DIN of the FPGA devices.
• The master FPGA DCLK output or external clock source drives the DCLK input of
the AT17A series configurator.
• The nCASC output of any AT17A series configurator drives the nCS input of the next
configurator in a cascaded chain of EEPROMs.
• SER_EN
must be connected to V
CC
(except during ISP).
Cascading Serial
Configuration
EEPROMs
For multiple FPGAs configured as a daisy-chain, or for FPGAs requiring larger configu-
ration memories, cascaded configurators provide additional memory.
After the last bit from the first configurator is read, the next clock signal to the configura-
tor asserts its nCASC output low and disables its DATA line driver. The second
configurator recognizes the low level on its nCS input and enables its DATA output.
After configuration is complete, the address counters of all cascaded configurators are
reset if the RESET/OE
on each configurator is driven to a Low level.
If the address counters are not to be reset upon completion, then the RESET/OE
input
canbetiedtoaHighlevel.
AT17A Series Reset
Polarity
The AT17A series configurator allows the user to program the polarity of the RESET/OE
pin as either RESET/OE or RESET/OE. This feature is supported by industry-standard
programmer algorithms.
Programming Mode The programming mode is entered by bringing SER_EN Low. In this mode the chip can
be programmed by the 2-wire serial bus. The programming is done at V
CC
supply only.
Programming super voltages are generated inside the chip.
Standby Mode The AT17LV65A/128A/256A enters a low-power standby mode whenever nCS is
asserted High. In this mode, the configurator consumes less than 50 µA of current
at 3.3V (100 µA for the AT17LV512A/010A/002A). The output remains in a high-imped-
ance state regardless of the state of the RESET/OE
input.
