MC74LVX257MELG

Semiconductor Components Industries, LLC, 2005
March, 2005 − Rev. 3
1 Publication Order Number:
MC74LVX257/D
MC74LVX257
Quad 2−Channel Multiplexer
with 3−State Outputs
The MC74LVX257 is an advanced high speed CMOS quad
2−channel multiplexer fabricated with silicon gate CMOS technology.
It consists of four 2−input digital multiplexers with common select
(S) and enable (OE) inputs. When (OE) is held High, selection of data
is inhibited and all the outputs go Low.
The select decoding determines whether the A or B inputs get routed
to the corresponding Y outputs.
The inputs tolerate voltages up to 7.0 V, allowing the interface of
5.0 V systems to 3.0 V systems.
Features
High Speed: t
PD
= 4.5 ns (Typ) at V
CC
= 3.3 V
Low Power Dissipation: I
CC
= 4 A (Max) at T
A
= 25°C
High Noise Immunity: V
NIH
= V
NIL
= 28% V
CC
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2.0 V to 5.5 V Operating Range
Low Noise: V
OLP
= 0.8 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
Chip Complexity: FETs = 100; Equivalent Gates = 25
ESD Performance:
Human Body Model > 2000 V;
Machine Model > 200 V
Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
http://onsemi.com
MARKING
DIAGRAMS
A = Assembly Location
WL or L = Wafer Lot
Y = Year
WW or W = Work Week
TSSOP−16
DT SUFFIX
CASE 948F
SOEIAJ−16
M SUFFIX
CASE 966
SOIC−16
D SUFFIX
CASE 751B
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
LVX257
AWLYWW
LVX
257
ALYW
LVX257
ALYW
1
16
1
16
1
16
MC74LVX257
http://onsemi.com
2
FUNCTION TABLE
OE S Y0 − Y3
A0 − A3, B0 − B3 = the levels
of the respective Data−Word
Inputs.
H
L
L
X
L
H
Z
A0A3
B0B3
Inputs
Outputs
3
OE
S
A0
B0
A1
B1
A2
B2
2
5
6
11
10
14
13
12
9
7
4
Y0
MUX
Y1
Y2
Y3
EN
1
15
A3
B3
G1
1
1
Figure 1. Pin Assignment
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
S
Y0
B0
A0
Y1
B1
A1
GND
Y3
B3
A3
OE
V
CC
B2
A2
Y2
Figure 2. Expanded Logic Diagram
Figure 3. IEC Logic Symbol
Za
I0a
4
2
S
I1a
3
1
Zb
I0b
7
5
I1b
6
Zc
I0c
12
14
I1c
13
Zd
I0d
9
11
I1d
10
OE
15
ORDERING INFORMATION
Device Package Shipping
MC74LVX257D SOIC−16 48 Units / Rail
MC74LVX257DG SOIC−16
(Pb−Free)
48 Units / Rail
MC74LVX257DR2 SOIC−16 2500 Tape & Reel
MC74LVX257DR2G SOIC−16
(Pb−Free)
2500 Tape & Reel
MC74LVX257DT TSSOP−16* 96 Units / Rail
MC74LVX257DTR2 TSSOP−16* 2500 Tape & Reel
MC74LVX257M SOEIAJ−16 50 Units / Rail
MC74LVX257MEL SOEIAJ−16 2000 Tape & Reel
MC74LVX257MELG SOEIAJ−16
(Pb−Free)
2000 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND (V
in
or V
out
) V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
MC74LVX257
http://onsemi.com
3
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
Positive DC Supply Voltage −0.5 to +7.0 V
V
IN
Digital Input Voltage −0.5 to +7.0 V
V
OUT
DC Output Voltage −0.5 to V
CC
+0.5 V
I
IK
Input Diode Current −20 mA
I
OK
Output Diode Current 20 mA
I
OUT
DC Output Current, per Pin 25 mA
I
CC
DC Supply Current, V
CC
and GND Pins 75 mA
P
D
Power Dissipation in Still Air SOIC Package
TSSOP
200
180
mW
T
STG
Storage Temperature Range −65 to +150 °C
V
ESD
ESD Withstand Voltage Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
>2000
>200
>2000
V
I
LATCHU
P
Latchup Performance Above V
CC
and Below GND at 125°C (Note 4) 300 mA
JA
Thermal Resistance, Junction−to−Ambient SOIC Package
TSSOP
143
164
°C/W
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. Tested to EIA/JESD22−A114−A
2. Tested to EIA/JESD22−A115−A
3. Tested to JESD22−C101−A
4. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol Characteristics Min Max Unit
V
CC
DC Supply Voltage 2.0 3.6 V
V
IN
DC Input Voltage 0 5.5 V
V
OUT
DC Output Voltage 0 V
CC
V
T
A
Operating Temperature Range, all Package
Types
−40 85 °C
t
r
, t
f
Input Rise or Fall Time V
CC
= 3.3 V + 0.3 V 0 100 ns/V

MC74LVX257MELG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Encoders, Decoders, Multiplexers & Demultiplexers 2-3.6V Quad 3-State 2-Channel
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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