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Fast Line Dump Timing
Figure 42. Fast Line Dump Timing
t
FD
t
VCCD
t
FD
t
VCCD
fFD
fV1
fV2
fH2
fH1
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Electronic Shutter
Electronic Shutter Line Timing
Figure 43. Electronic Shutter Line Timing
t
HD
t
VCCD
VSUB
fV1
fV2
fH2
fH1
t
SD
t
S
fR
V
SHUTTER
Electronic Shutter Integration Time Definition
Figure 44. Integration Time Definition
VSUB
fV2
V
SHUTTER
Integration Time
Electronic Shutter DC and AC Bias Definition
The figure below shows the DC bias (VSUB) and AC clock (VES) applied to the SUB pin. Both the DC bias and AC clock
are referenced to ground.
Figure 45. DC Bias and AC Clock Applied to the SUB Pin
SUB
GND GND
V
SHUTTER
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Electronic Shutter Description
The voltage on the substrate (SUB) determines the charge
capacity of the photodiodes. When SUB is 8 V the
photodiodes will be at their maximum charge capacity.
Increasing VSUB above 8 V decreases the charge capacity
of the photodiodes until 48 V when the photodiodes have
a charge capacity of zero electrons. Therefore, a short pulse
on SUB, with a peak amplitude greater than 48 V, empties
all photodiodes and provides the electronic shuttering
action.
It may appear the optimal substrate voltage setting is 8 V
to obtain the maximum charge capacity and dynamic range.
While setting VSUB to 8 V will provide the maximum
dynamic range, it will also provide the minimum
anti-blooming protection.
The KAI4011 VCCD has a charge capacity of
60,000 electrons (60 ke
). If the SUB voltage is set such that
the photodiode holds more than 60 ke
, then when the
charge is transferred from a full photodiode to VCCD,
the VCCD will overflow. This overflow condition manifests
itself in the image by making bright spots appear elongated
in the vertical direction. The size increase of a bright spot is
called blooming when the spot doubles in size.
The blooming can be eliminated by increasing the voltage
on SUB to lower the charge capacity of the photodiode. This
ensures the VCCD charge capacity is greater than the
photodiode capacity. There are cases where an extremely
bright spot will still cause blooming in the VCCD. Normally,
when the photodiode is full, any additional electrons
generated by photons will spill out of the photodiode.
The excess electrons are drained harmlessly out to the
substrate. There is a maximum rate at which the electrons
can be drained to the substrate. If that maximum rate is
exceeded, (for example, by a very bright light source) then
it is possible for the total amount of charge in the photodiode
to exceed the VCCD capacity. This results in blooming.
The amount of anti-blooming protection also decreases
when the integration time is decreased. There is
a compromise between photodiode dynamic range
(controlled by VSUB) and the amount of anti-blooming
protection. A low VSUB voltage provides the maximum
dynamic range and minimum (or no) anti-blooming
protection. A high VSUB voltage provides lower dynamic
range and maximum anti-blooming protection. The optimal
setting of VSUB is written on the container in which each
KAI4011 is shipped. The given VSUB voltage for each
sensor is selected to provide anti-blooming protection for
bright spots at least 100 times saturation, while maintaining
at least 40 ke
of dynamic range.
The electronic shutter provides a method of precisely
controlling the image exposure time without any
mechanical components. If an integration time of t
INT
is
desired, then the substrate voltage of the sensor is pulsed to
at least 40 V t
INT
seconds before the photodiode to VCCD
transfer pulse on V2. Use of the electronic shutter does not
have to wait until the previously acquired image has been
completely read out of the VCCD.
Large Signal Output
When the image sensor is operated in the binned or
summed interlaced modes there will be more than
40,000 electrons in the output signal. The image sensor is
designed with a 16 mV/e charge to voltage conversion on the
output. This means a full signal of 40,000 electrons will
produce a 640 mV change on the output amplifier.
The output amplifier was designed to handle an output
swing of 640 mV at a pixel rate of 40 MHz. If 80,000
electron charge packets are generated in the binned or
summed interlaced modes then the output amplifier output
will have to swing 1,280 mV. The output amplifier does not
have enough bandwidth (slew rate) to handle 1,280 mV at
40 MHz. Hence, the pixel rate will have to be reduced to
20 MHz if the full dynamic range of 80,000 electrons is
desired.
The charge handling capacity of the output amplifier is
also set by the reset clock voltage levels. The reset clock
driver circuit is very simple if an amplitude of 5 V is used.
But the 5 V amplitude restricts the output amplifier charge
capacity to 40,000 electrons. If the full dynamic range of
80,000 electrons is desired then the reset clock amplitude
will have to be increased to 7 V.
If you only want a maximum signal of 40,000 electrons in
binned or summed interlaced modes, then a 40 MHz pixel
rate with a 5 V reset clock may be used. The output of the
amplifier will be unpredictable above 40,000 electrons so be
sure to set the maximum input signal level of your analog to
digital converter to the equivalent of 40,000 electrons
(640 mV).

KAI-4011-AAA-CR-BA

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Image Sensors INTERLINE CCD IMAGE SENSOR
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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