KAI−4011
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6
Horizontal Register to Floating Diffusion
Figure 5. Horizontal Register to Floating Diffusion Architecture
n+
R OG H2S H1S H1B H2S H2B H1S
n− n− n−
RD
Floating
Diffusion
n (burried channel)
n
n+
p (GND)
n (SUB)
H2B
The HCCD has a total of 2124 pixels. The 2112 vertical
shift registers (columns) are shifted into the center 2112
pixels of the HCCD. There are 12 pixels at both ends of the
HCCD, which receive no charge from a vertical shift
register. The first 12 clock cycles of the HCCD will be empty
pixels (containing no electrons). The next 28 clock cycles
will contain only electrons generated by dark current in the
VCCD and photodiodes. The next 2056 clock cycles will
contain photo−electrons (image data). Finally, the last 28
clock cycles will contain only electrons generated by dark
current in the VCCD and photodiodes. Of the 28 dark
columns, the first and last dark columns should not be used
for determining the zero signal level. Some light does leak
into the first and last dark columns. Only use the center 26
columns of the 28 column dark reference.
When the HCCD is shifting valid image data, the timing
inputs to the electronic shutter (SUB), VCCD (V1, V2), and
fast line dump (FD) should be not be pulsed. This prevents
unwanted noise from being introduced. The HCCD is a type
of charge coupled device known as a pseudo−two phase
CCD. This type of CCD has the ability to shift charge in two
directions. This allows the entire image to be shifted out to
the video L output, or to the video R output (left/right image
reversal). The HCCD is split into two equal halves of 1068
pixels each. When operating the sensor in single output
mode the two halves of the HCCD are shifted in the same
direction. When operating the sensor in dual output mode
the two halves of the HCCD are shifted in opposite
directions. The direction of charge transfer in each half is
controlled by the H1BL, H2BL, H1BR, and H2BR timing
inputs.
