4
4510J–RKE–12/08
T5753
3. General Description
This fully integrated PLL transmitter allows particularly simple, low-cost RF miniature transmit-
ters to be assembled. The VCO is locked to 32 f
XTAL
hence a 9.8438 MHz crystal is needed for a
315 MHz transmitter. All other PLL and VCO peripheral elements are integrated.
The XTO is a series resonance oscillator so that only one capacitor together with a crystal con-
nected in series to GND are needed as external elements.
The crystal oscillator together with the PLL needs typically < 3 ms until the PLL is locked and the
CLK output is stable. There is a wait time of 3 ms until the CLK is used for the microcontroller
and the PA is switched on.
The power amplifier is an open-collector output delivering a current pulse which is nearly inde-
pendent from the load impedance. The delivered output power is hence controllable via the
connected load impedance.
This output configuration enables a simple matching to any kind of antenna or to 50 Ω. A high
power efficiency of η=P
out
/(I
S,PA
V
S
) of 40% for the power amplifier results when an optimized
load impedance of Z
Load
= (255 + j192) Ω is used at 3 V supply voltage.
4. Functional Description
If ENABLE = L and the PA_ENABLE = L, the circuit is in standby mode consuming only a very
small amount of current so that a lithium cell used as power supply can work for several years.
With ENABLE = H the XTO, PLL and the CLK driver are switched on. If PA_ENABLE remains L
only the PLL and the XTO is running and the CLK signal is delivered to the microcontroller. The
VCO locks to 32 times the XTO frequency.
With ENABLE = H and PA_ENABLE = H the PLL, XTO, CLK driver and the power amplifier are
on. With PA_ENABLE the power amplifier can be switched on and off, which is used to perform
the ASK modulation.
4.1 ASK Transmission
The T5753 is activated by ENABLE = H. PA_ENABLE must remain L for typically 3ms, then
the CLK signal can be taken to clock the microcontroller and the output power can be modulated
by means of Pin PA_ENABLE. After transmission PA_ENABLE is switched to L and the micro-
controller switches back to internal clocking. The T5753 is switched back to standby mode with
ENABLE = L.
4.2 FSK Transmission
The T5753 is activated by ENABLE = H. PA_ENABLE must remain L for typically 3ms, then
the CLK signal can be taken to clock the microcontroller and the power amplifier is switched on
with PA_ENABLE = H. The chip is then ready for FSK modulation. The microcontroller starts to
switch on and off the capacitor between the XTAL load capacitor and GND with an open-drain
output port, thus changing the reference frequency of the PLL. If the switch is closed, the output
frequency is lower than if the switch is open. After transmission PA_ENABLE is switched to L
and the microcontroller switches back to internal clocking. The T5753 is switched back to
standby mode with ENABLE = L.
The accuracy of the frequency deviation with XTAL pulling method is about ±25% when the fol-
lowing tolerances are considered.
5
4510J–RKE–12/08
T5753
Figure 4-1. Tolerances of Frequency Modulation
Using C
4
=8.2p5%, C
5
= 10 pF ±5%, a switch port with C
Switch
= 3 pF ±10%, stray capaci-
tances on each side of the crystal of C
Stray1
=C
Stray2
= 1 pF ±10%, a parallel capacitance of the
crystal of C
0
= 3.2 pF ±10% and a crystal with C
M
= 13 fF ±10%, an FSK deviation of ±21.5 kHz
typical with worst case tolerances of ±16.25 kHz to ±28.01 kHz results.
4.3 CLK Output
An output CLK signal is provided for a connected microcontroller, the delivered signal is CMOS
compatible if the load capacitance is lower than 10 pF.
4.3.1 Clock Pulse Take-over
The clock of the crystal oscillator can be used for clocking the microcontroller. Atmel
®
’s
ATARx9x has the special feature of starting with an integrated RC-oscillator to switch on the
T5753 with ENABLE = H, and after 3 ms to assume the clock signal of the transmission IC, so
that the message can be sent with crystal accuracy.
4.3.2 Output Matching and Power Setting
The output power is set by the load impedance of the antenna. The maximum output power is
achieved with a load impedance of Z
Load,opt
= (255 + j192)Ω. There must be a low resistive path
to V
S
to deliver the DC current.
The delivered current pulse of the power amplifier is 9 mA and the maximum output power is
delivered to a resistive load of 400Ω if the 1.0 pF output capacitance of the power amplifier is
compensated by the load impedance.
An optimum load impedance of:
Z
Load
=400Ω || j/(2 ×π1.0pF)=(255+j192)Ω thus results for the maximum output power of
8dBm.
The load impedance is defined as the impedance seen from the T5753’s ANT1, ANT2 into the
matching network. Do not confuse this large signal load impedance with a small signal input
impedance delivered as input characteristic of RF amplifiers and measured from the application
into the IC instead of from the IC into the application for a power amplifier.
Less output power is achieved by lowering the real parallel part of 400Ω where the parallel imag-
inary part should be kept constant.
Output power measurement can be done with the circuit of Figure 4-2. Note that the component
values must be changed to compensate the individual board parasitics until the T5753 has the
right load impedance Z
Load,opt
= (255 + j192)Ω. Also the damping of the cable used to measure
the output power must be calibrated out.
R
S
L
M
C
4
C
M
V
S
XTAL
Crystal equivalent circuit
C
0
C
5
C
Switch
C
Stray1
C
Stray2
6
4510J–RKE–12/08
T5753
Figure 4-2. Output Power Measurement at f = 315 MHz
Note: For 345 MHz C
2
has to be changed to 2.7 pF
4.4 Application Circuit
For the blocking of the supply voltage a capacitor value of C
3
= 68 nF/X7R is recommended
(see Figure 4-3 on page 7 and Figure 4-4 on page 8). C
1
and C
2
are used to match the loop
antenna to the power amplifier where C
1
typically is 22 pF/NP0 and C
2
is 10.8 pF/NP0
(18 pF + 27 pF in series); for C
2
two capacitors in series should be used to achieve a better tol-
erance value and to have the possibility to realize the Z
Load,opt
by using standard valued
capacitors.
C
1
forms together with the pins of T5753 and the PCB board wires a series resonance loop that
suppresses the 1
st
harmonic, hence the position of C
1
on the PCB is important. Normally the
best suppression is achieved when C
1
is placed as close as possible to the pins ANT1 and
ANT2.
The loop antenna should not exceed a width of 1.5 mm, otherwise the Q-factor of the loop
antenna is too high.
L
1
([50 nH to 100 nH) can be printed on PCB. C
4
should be selected that the XTO runs on the
load resonance frequency of the crystal. Normally, a value of 12 pF results for a 15 pF
load-capacitance crystal.
1 nF
3.3 pF
56 nH
C
1
C
2
L
1
V
S
R
in
ANT2
ANT1
Z
Lopt
Power
meter
50Ω
Z = 50Ω

T5753-6AP

Mfr. #:
Manufacturer:
Description:
RF TX IC ASK 310-350MHZ 8TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet