CA3420E

4
FN1320.9
October 4, 2005
Typical Performance Curves
FIGURE 3. OUTPUT VOLTAGE SWING AND COMMON MODE
INPUT VOLTAGE RANGE vs SUPPLY VOLTAGE
FIGURE 4. OUTPUT VOLTAGE vs LOAD SOURCING CURRENT
FIGURE 5. OUTPUT VOLTAGE vs LOAD SINKING CURRENT FIGURE 6. INPUT NOISE VOLTAGE vs FREQUENCY
FIGURE 7. OPEN LOOP GAIN AND PHASE SHIFT RESPONSE
V
O
-
R
L
= 100k
10
SUPPLY VOLTAGE (V)
15
T
A
= 25°C
-1.0
INPUT & OUTPUT VOLTAGE EXCURSIONS FROM THE
V
O
+
V
ICR
-
V
ICR
+
510
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
POSITIVE AND NEGATIVE SUPPLY VOLTAGE (V)
V+ = 2V
V+ = 5V
V+ = 10V
V+ = 20V
1010.10.01
LOAD (SOURCING) CURRENT (mA)
V- = 0V
T
A
= 25°C
1000
100
10
OUTPUT STAGE TRANSISTOR SATURATION
VOLTAGE, Q
19
(mV)
V- = -2V
V- = -5V
V- = -10V
V- = -20V
1010.10.01
LOAD (SINKING) CURRENT (mA)
10
100
1000
OUTPUT STAGE TRANSISTOR SATURATION
VOLTAGE, Q
17
(mV)
V+ = 0V
T
A
= 25°C
V
S
= ±10V
V
S
= ±5V
V
S
= ±1V
10
6
FREQUENCY (Hz)
10
5
10
4
10
3
10
2
10
1
1
10
100
1000
T
A
= 25°C
EQUIVALENT INPUT NOISE VOLTAGE (nV/Hz)
FREQUENCY (Hz)
10
6
10
5
10
4
10
2
10
1
1
10
3
V
S
= ±5V
T
A
= 25°C
R
L
= 10k
C
L
= 0pF
0
20
40
60
80
100
-180
-135
-90
-45
0
OPEN LOOP VOLTAGE GAIN (dB)
OPEN LOOP PHASE (DEGREES)
CA3420
5
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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FN1320.9
October 4, 2005
CA3420
Dual-In-Line Plastic Packages (PDIP)
C
L
E
e
A
C
e
B
e
C
-B-
E1
INDEX
12 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1
B
e
D
D1
A
A2
L
A
1
-A-
0.010 (0.25) C AM BS
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated
in JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protru-
sions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
6. E and are measured with the leads constrained to be per-
pendicular to datum .
7. e
B
and e
C
are measured at the lead tips with the leads uncon-
strained. e
C
must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
e
A
-C-
E8.3 (JEDEC MS-001-BA ISSUE D)
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A-0.210 - 5.33 4
A1 0.015 - 0.39 -4
A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.15 1.77 8, 10
C 0.008 0.014 0.204 0.355 -
D 0.355 0.400 9.01 10.16 5
D1 0.005 - 0.13 -5
E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
e
A
0.300 BSC 7.62 BSC 6
e
B
- 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N8 89
Rev. 0 12/93

CA3420E

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
IC OPAMP GP 1 CIRCUIT 8DIP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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