RoboClockII™ Junior,
CY7B9930V, CY7B9940V
Document Number: 38-07271 Rev. *E Page 3 of 12
Logic Block Diagram Description
Phase Frequency Detector and Filter
These two blocks accept signals from the REF inputs (REFA+,
REFA–, REFB+ or REFB–) and the FB input (FBKA). Correction
information is then generated to control the frequency of the
Voltage Controlled Oscillator (VCO). These two blocks, along
with the VCO, form a Phase-Locked Loop (PLL) that tracks the
incoming REF signal.
The RoboClockII™ Junior has a flexible REF input scheme.
These inputs allow the use of either differential LVPECL or single
ended LVTTL inputs. To configure as single ended LVTTL inputs,
leave the complementary pin to 1.5V), then use the other input
pin as an LVTTL input. The REF inputs are also tolerant to hot
insertion.
The REF inputs can be changed dynamically. When changing
from one reference input to the other reference input of the same
frequency, the PLL is optimized to ensure that the clock outputs
period is not less than the calculated system budget (t
MIN
= t
REF
(nominal reference clock period) – t
CCJ
(cycle-to-cycle jitter) –
t
PDEV
(max. period deviation)) while reacquiring lock.
VCO, Control Logic, and Divide Generator
The VCO accepts analog control inputs from the PLL filter block.
The FS control pin setting determines the nominal operational
frequency range of the divide by one output (f
NOM
) of the device.
f
NOM
is directly related to the VCO frequency. There are two
versions of the RoboClockII Junior, a low speed device
(CY7B9930V) where f
NOM
ranges from 12 MHz to 100 MHz, and
a high speed device (CY7B9940V), which ranges from 24 MHz
to 200 MHz. The FS setting for each device is shown in Table 1.
The f
NOM
frequency is seen on “divide-by-one” outputs.
Divide Matrix
The Divide Matrix is comprised of three independent banks: two
banks of clock outputs and one bank for feedback. Each clock
output bank has two pairs of low-skew, high fanout output buffers
([1:2]Q[A:B][0:1]), and an output disable (DIS[1:2]).
The feedback bank has one pair of low-skew, high fanout output
buffers (QFA[0:1]). One of these outputs may connect to the
selected feedback input (FBKA+). This feedback bank also has
two divider function selects FBDS[0:1].
The divide capabilities for each bank are shown in Table 2.
Output Disable Description
The outputs of Bank 1 and Bank 2 can be independently put into
a HOLD OFF or high impedance state. The combination of the
Output_Mode and DIS[1:2] inputs determines the clock outputs’
state for each bank. When the DIS[1:2] is LOW, the outputs of
the corresponding bank are enabled. When the DIS[1:2] is HIGH,
the outputs for that bank are disabled to a high impedance (HI-Z)
or HOLD OFF state depending on the Output_Mode input.
Table 3 defines the disabled output functions.
Table 1. Frequency Range Select
FS
[1]
CY7B9930V CY7B9940V
f
NOM
(MHz) f
NOM
(MHz)
Min. Max. Min. Max.
LOW 12 26 24 52
MID 24 52 48 100
HIGH 48 100 96 200
[2]
Notes
1. The level to be set on FS is determined by the “nominal” operating frequency (f
NOM
) of the V
CO
. f
NOM
always appears on an output when the output is operating in
the undivided mode. The REF and FB are at f
NOM
when the output connected to FB is undivided.
2. The maximum output frequency is 200 MHz.
Table 2. Output Divider Function
Function
Selects
Output Divider Function
FBDS1 FBDS0 Bank 1 Bank 2
Feedback
Bank
LOW LOW /1 /1 /1
LOW MID /1 /1 /2
LOW HIGH /1 /1 /3
MID LOW /1 /1 /4
MID MID /1 /1 /5
MID HIGH /1 /1 /6
HIGH LOW /1 /1 /8
HIGH MID /1 /1 /10
HIGH HIGH /1 /1 /12
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