CY7B9940V-5AXIT

RoboClockII™ Junior,
CY7B9930V, CY7B9940V
Document Number: 38-07271 Rev. *E Page 7 of 12
Operating Current
I
CCI
Internal operating
current
CY7B9930V V
CC
= Max., f
MAX
[5]
200 mA
CY7B9940V 200 mA
I
CCN
Output current
dissipation/pair
[6]
CY7B9930V V
CC
= Max.,
C
LOAD
= 25 pF,
R
LOAD
= 50Ω at V
CC
/2,
f
MAX
–40mA
CY7B9940V 50 mA
Capacitance
Parameter Description Test Conditions Min. Max. Unit
C
IN
Input capacitance T
A
= 25°C, f = 1 MHz, V
CC
= 3.3V 5 pF
Switching Characteristics
Over the Operating Range
[7, 8, 9, 10, 11]
Parameter Description
CY7B9930/40V-2 CY7B9930/40V-5
Unit
Min. Max. Min. Max.
f
in
Clock input frequency CY7B9930V 12 100 12 100 MHz
CY7B9940V 24 200 24 200 MHz
f
out
Clock input frequency CY7B9930V 12 100 12 100 MHz
CY7B9940V 24 200 24 200 MHz
t
SKEWPR
Matched pair skew
[12, 13]
–185–185 ps
t
SKEWBNK
Intrabank skew
[12, 13]
–200–250 ps
t
SKEW0
Output-Output skew (same frequency and phase, rise to rise, fall
to fall)
[12, 13]
–250–550 ps
t
SKEW1
Output-Output skew (same frequency and phase, other banks at
different frequency, rise to rise, fall to fall)
[12, 13]
–250–650 ps
t
CCJ1-3
Cycle-to-cycle jitter (divide by 1 output frequency,
FB = divide by 1, 2, 3)
150 150 ps Peak-
Peak
t
CCJ4-12
Cycle-to-cycle jitter (divide by 1 output frequency,
FB = divide by 4, 5, 6, 8, 10, 12)
100 100 ps Peak-
Peak
t
PD
Propagation delay, REF to FB Rise –250 250 –500 500 ps
t
PDDELTA
Propagation delay difference between two devices
[14]
200 200 ps
t
REFpwh
REF input (pulse width HIGH)
[15]
2.0–2.0– ns
t
REFpwl
REF input (pulse width LOW)
[15]
2.0–2.0– ns
t
r
/t
f
Output rise/fall time
[16]
0.15 2.0 0.15 2.0 ns
Notes
5. I
CCI
measurement is performed with Bank1 and FB Bank configured to run at maximum frequency (f
NOM
= 100 MHz for CY7B9930V, f
NOM
= 200 MHz for CY7B9940V),
and all other clock output banks to run at half the maximum frequency. FS and OUTPUT_MODE are asserted to the HIGH state.
6. This is dependent upon frequency and number of outputs of a bank being loaded. The value indicates maximum I
CCN
at maximum frequency and maximum load of
25 pF terminated to 50Ω at V
CC
/2.
7. This is for non-three level inputs.
8. Assumes 25 pF Max. Load Capacitance up to 185 Mhz. At 200 MHz the max load is 10 pF.
9. Both outputs of pair must be terminated, even if only one is being used.
10. Each package must be properly decoupled.
11. AC parameters are measured at 1.5V, unless otherwise indicated.
12. Test Load C
L
= 25 pF, terminated to V
CC
/2 with 50Ω.
13. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same phase delay has been selected when all outputs
are loaded with 25 pF and properly terminated up to 185 MHz. At 200 MHz the max load is 10 pF.
14. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
15. Tested initially and after any design or process changes that may affect these parameters.
16. Rise and fall times are measured between 2.0V and 0.8V.
Electrical Characteristics Over the Operating Range (continued)
Parameter Description Test Conditions Min. Max. Unit
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RoboClockII™ Junior,
CY7B9930V, CY7B9940V
Document Number: 38-07271 Rev. *E Page 8 of 12
Figure 1. AC Test Loads and Waveform
[22]
t
LOCK
PLL lock time from power up 10 10 ms
t
RELOCK1
PLL relock time (from same frequency, different phase) with
stable power supply
–500–500 μs
t
RELOCK2
PLL Relock Time (from different frequency, different phase) with
Stable Power Supply
[17]
1000 1000 μs
t
ODCV
Output duty cycle deviation from 50%
[11]
–1.0 1.0 –1.0 1.0 ns
t
PWH
Output HIGH time deviation from 50%
[18]
–1.5–1.5 ns
t
PWL
Output LOW time deviation from 50%
[18]
–2.0–2.0 ns
t
PDEV
Period deviation when changing from reference to reference
[19]
0.025 0.025 UI
t
OAZ
DIS[1:2] HIGH to output high impedance from ACTIVE
[12, 20]
1.0101.010 ns
t
OZA
DIS[1:2] LOW to output ACTIVE from output is high
impedance
[20, 21]
0.5140.514 ns
Switching Characteristics
Over the Operating Range
[7, 8, 9, 10, 11]
(continued)
Parameter Description
CY7B9930/40V-2 CY7B9930/40V-5
Unit
Min. Max. Min. Max.
2.0V
0.8V
3.3V
GND
2.0V
0.8V
3.3V
OUTPUT
(a) LVTTL
AC Test Load
< 1ns < 1 ns
(b)TTL Input Test Waveform
R1
R2
C
L
R1 = 910
Ω
R2 = 910
Ω
C
L
<30pF
(Includes fixture and
probe capacitance)
R1 = 100Ω
R2 = 100Ω
C
L
< 25 pF up to 185 MHz
For LOCK output only For all other outputs
10 pF from 185 to 200 MHz
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RoboClockII™ Junior,
CY7B9930V, CY7B9940V
Document Number: 38-07271 Rev. *E Page 9 of 12
AC Timing Diagrams
See note. [11]
t
PWL
t
PWH
REF
FB
Q
t
REFpwh
t
REFpwl
t
PD
t
CCJ1-3,4-12
[1:4]Q[A:B]0
[1:4]Q[A:B]1
t
SKEWPR
[1:4]QA[0:1]
[1:4]QB[0:1]
t
SKEWBNK
t
SKEWPR
t
SKEWBNK
Q
Other Q
t
SKEW0,1
t
SKEW0,1
2.0V
0.8V
QFA0 or
QFA1 or
t
ODCV
t
ODCV
REF TO DEVICE 1 and 2
FB DEVICE1
FB DEVICE2
t
PD
t
PDELTA
t
PDELTA
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CY7B9940V-5AXIT

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
Phase Locked Loops - PLL 3.3V 200MHz 10 Outputs
Lifecycle:
New from this manufacturer.
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