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7006S55PF8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
10
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing
(1,5,8)
Timing Waveform of Write Cycle No. 2, CE Controlled Timing
(1,5)
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (t
EW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.
3. t
WR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W low transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured by 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of t
WP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed
on the bus for the required t
DW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified
t
WP.
9. To access RAM, CE = V
IL and SEM = VIH. To access semaphore CE = VIH and SEM = VIL. tEW must be met for either condition.
R/W
t
WC
t
HZ
(7)
t
AW
t
WR
(3)
t
AS
(6)
t
WP
(2)
DATA
OUT
t
WZ
(7)
t
DW
t
DH
t
OW
OE
ADDRESS
DATA
IN
(4) (4)
2739 drw 09
CE
or
SEM
(9)
2739 drw 10
t
WC
t
AS
(6)
t
WR
(3)
t
DW
t
DH
ADDRESS
DATA
IN
CE
or
SEM
(9)
R/W
t
AW
t
EW
(2)
6.42
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
11
Timing Waveform of Semaphore Read after Write Timing, Either Side
(1)
NOTE:
1. CE = V
IH for the duration of the above timing (both write and read cycle).
NOTES:
1. D
OR = DOL = VIL, CER = CEL = VIH, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.
2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
3. This parameter is measured from R/W
"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If t
SPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
Timing Waveform of Semaphore Write Contention
(1,3,4)
SEM
2739 drw 11
t
AW
t
EW
t
SOP
DATA
0
VALID ADDRESS
t
SAA
R/W
t
WR
t
OH
t
ACE
VALID ADDRESS
DATA
IN
VALID
t
DW
t
WP
t
DH
t
AS
t
SWRD
t
AOE
t
SOP
Read Cycle
Write Cycle
A
0
-A
2
OE
DATA
OUT
VALID
SEM
"A"
2739 drw 12
t
SPS
MATCH
R/W
"A"
MATCH
A
0"A"
-A
2"A"
SIDE “A”
(2)
SEM
"B"
R/W
"B"
A
0"B"
-A
2"B"
SIDE
“B”
(2)
12
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY".
2. To ensure that the earlier of the two ports wins.
3. t
BDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited with port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention with port "A".
6. 'X' is part numbers indicates power rating (S or L).
.
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(6)
7006X15
Com'l Only
7006X17
Com'l Only
7006X20
Com'l, Ind
& Military
7006X25
Com'l &
Military
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
BUSY TIMING (M/S=V
IH
)
t
BAA
BUSY Access Time from Address Match
____
15
____
17
____
20
____
20 ns
t
BDA
BUSY Disable Time from Address Not Matched
____
15
____
17
____
20
____
20 ns
t
BAC
BUSY Access Time from Chip Enable Low
____
15
____
17
____
20
____
20 ns
t
BDC
BUSY Access Time from Chip Enable High
____
15
____
17
____
17
____
17 ns
t
APS
Arbitration Priority Set-up Time
(2)
5
____
5
____
5
____
5
____
ns
t
BDD
BUSY Disable to Valid Data
(3)
____
18
____
18
____
30
____
30 ns
t
WH
Write Hold After BUSY
(5 )
12
____
13
____
15
____
17
____
ns
BUSY TIMING (M/S=V
IL
)
t
WB
BUSY Input to Write
(4)
0
____
0
____
0
____
0
____
ns
t
WH
Write Hold After BUSY
(5 )
12
____
13
____
15
____
17
____
ns
PORT-TO-PORT DELAY TIMING
t
WDD
Write Pulse to Data Delay
(1)
____
30
____
30
____
45
____
50 ns
t
DD D
Write Data Valid to Read Data Delay
(1 )
____
25
____
25
____
35
____
35 ns
2739 tbl 15a
7006X35 Com'l
& Military
7006X55
Com'l, Ind
& Military
7006X70
Military
Only
Symbol Parameter Min.Max.Min.Max.Min.Max.Unit
BUSY TIMING (M/S=V
IH
)
t
BAA
BUSY Access Time from Address Match
____
20
____
45
____
45 ns
t
BDA
BUSY Disable Time from Address Not Matched
____
20
____
40
____
40 ns
t
BAC
BUSY Access Time from Chip Enable Low
____
20
____
40
____
40 ns
t
BDC
BUSY Access Time from Chip Enable High
____
20
____
35
____
35 ns
t
APS
Arbitration Priority Set-up Time
(2 )
5
____
5
____
5
____
ns
t
BDD
BUSY Disable to Valid Data
(3 )
____
35
____
40
____
45 ns
t
WH
Write Hold After BUSY
(5 )
25
____
25
____
25
____
ns
BUSY TIMING (M/S=V
IL
)
t
WB
BUSY Input to Write
(4 )
0
____
0
____
0
____
ns
t
WH
Write Hold After BUSY
(5 )
25
____
25
____
25
____
ns
PORT-TO-PORT DELAY TIMING
t
WDD
Write Pulse to Data Delay
(1 )
____
60
____
80
____
95 ns
t
DD D
Write Data Valid to Read Data Delay
(1 )
____
45
____
65
____
80 ns
2739 tbl 15b
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

7006S55PF8

Mfr. #:
Buy 7006S55PF8
Manufacturer:
IDT
Description:
SRAM 16K X 8 DUAL PORT SRAM
Lifecycle:
New from this manufacturer.
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