6.42
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
7
AC Test Conditions
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with load (Figures 1 and 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = V
IL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL.
4. 'X' in part numbers indicates power rating (S or L).
Figure 2. Output Test Load
(5pF for t
LZ, tHZ, tWZ, tOW)
*Including scope and jig.
Figure 1. AC Output Test Load
AC Electrical Oharacteristics Over the
Operating temperature and Supply Voltage Range
(4)
1250Ω
30pF
775Ω
DATA
OUT
BUSY
INT
5V
5V
1250Ω
5pF*
775Ω
DATA
OUT
2739 drw 06
,
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns Max.
1.5V
1.5V
Figures 1 and 2
2739 tbl 12
7006X15
Com'l Only
7006X17
Com'l Only
7006X20
Com'l,Ind
& Military
7006X25
Com'l & Military
UnitSymbol Parameter Min. Max. Min. Max. Min. Max. Min. Max.
READ CYCLE
t
RC
Read Cycle Time 15
____
17
____
20
____
25
____
ns
t
AA
Address Access Time
____
15
____
17
____
20
____
25 ns
t
ACE
Chip Enable Access Time
(3)
____
15
____
17
____
20
____
25 ns
t
AOE
Output Enable Access Time
____
10
____
10
____
12
____
13 ns
t
OH
Output Hold from Address Change 3
____
3
____
3
____
3
____
ns
t
LZ
Output Low-Z Time
(1,2)
3
____
3
____
3
____
3
____
ns
t
HZ
Output High-Z Time
(1,2)
____
10
____
10
____
12
____
15 ns
t
PU
Chip Enable to Power Up Time
(2,5)
0
____
0
____
0
____
0
____
ns
t
PD
Chip Disable to Power Down Time
(2,5)
____
15
____
17
____
20
____
25 ns
t
SOP
Semaphore Flag Update Pulse (OE or SEM)10
____
10
____
10
____
10
____
ns
t
SAA
Semaphore Address Access Time
____
15
____
17
____
20
____
25 ns
2739 tbl 13a
7006X35
Com'l &
Military
7006X55
Com'l, Ind
& Military
7006X70
Military
Only
UnitSymbol Parameter Min.Max.Min.Max.Min.Max.
READ CYCLE
t
RC
Read Cycle Time 35
____
55
____
70
____
ns
t
AA
Address Access Time
____
35
____
55
____
70 ns
t
ACE
Chip Enable Access Time
(3)
____
35
____
55
____
70 ns
t
AOE
Output Enable Access Time
____
20
____
30
____
35 ns
t
OH
Output Hold from Address Change 3
____
3
____
3
____
ns
t
LZ
Output Low-Z Time
(1,2)
3
____
3
____
3
____
ns
t
HZ
Output High-Z Time
(1,2)
____
15
____
25
____
30 ns
t
PU
Chip Enable to Power Up Time
(2,5)
0
____
0
____
0
____
ns
t
PD
Chip Disable to Power Down Time
(2,5)
____
35
____
50
____
50 ns
t
SOP
Semaphore Flag Update Pulse (OE or SEM)15
____
15
____
15
____
ns
t
SAA
Semaphore Address Access Time
____
35
____
55
____
70 ns
2739 tbl 13b
8
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
Timing of Power-Up Power-Down
Waveform of Read Cycles
(5)
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first CE or OE.
3. t
BDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last t
AOE, tACE, tAA or tBDD.
5. SEM = V
IH.
t
RC
R/W
CE
ADDR
t
AA
(4)
OE
2739 drw 07
t
ACE
(4)
t
AOE
(4)
t
LZ
(1)
t
OH
t
HZ
(2)
t
BDD
(3,4)
DATA
OUT
BUSY
OUT
VALID DATA
(4)
CE
2739 drw 08
t
PU
I
CC
I
SB
t
PD
,
6.42
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
9
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested but not tested.
3. To access RAM, CE = V
IL, SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for t
DH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage
and temperature, the actual t
DH will always be smaller than the actual tOW.
5. 'X' in part numbers indicates power rating (S or L).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage
(5)
Symbol Parameter
7006X15
Com'l Only
7006X17
Com'l Only
7006X20
Com'l, Ind
& Military
7006X25
Com'l &
Military
UnitMin. Max. Min. Max. Min. Max. Min. Max.
WRITE CYCLE
t
WC
Write Cycle Time 15
____
17
____
20
____
25
____
ns
t
EW
Chip Enable to End-of-Write
(3)
12
____
12
____
15
____
20
____
ns
t
AW
Address Valid to End-of-Write 12
____
12
____
15
____
20
____
ns
t
AS
Address Set-up Time
(3)
0
____
0
____
0
____
0
____
ns
t
WP
Write Pulse Width 12
____
12
____
15
____
20
____
ns
t
WR
Write Recovery Time 0
____
0
____
0
____
0
____
ns
t
DW
Data Valid to End-of-Write 10
____
10
____
15
____
15
____
ns
t
HZ
Output High-Z Time
(1,2)
____
10
____
10
____
12
____
15 ns
t
DH
Data Hold Time
(4)
0
____
0
____
0
____
0
____
ns
t
WZ
Write Enable to Output in High-Z
(1,2)
____ ____ ____ ____ ____
12
____
15 ns
t
OW
Output Active from End-of-Write
(1, 2 ,4 )
0
____
0
____
0
____
0
____
ns
t
SWRD
SEM Flag Write to Read Time
5
____
5
____
5
____
5
____
ns
t
SPS
SEM Flag Contention Window
5
____
5
____
5
____
5
____
ns
2739 tbl 14a
Symbol Parameter
7006X35
Com'l & Military
7006X55
Com'l, Ind
& Military
7006X70
Military
Only
UnitMin. Max. Min. Max. Min. Max.
WRITE CYCLE
t
WC
Write Cycle Time 35
____
55
____
70
____
ns
t
EW
Chip Enable to End-of-Write
(3)
30
____
45
____
50
____
ns
t
AW
Address Valid to End-of-Write 30
____
45
____
50
____
ns
t
AS
Address Set-up Time
(3)
0
____
0
____
0
____
ns
t
WP
Write Pulse Width 25
____
40
____
50
____
ns
t
WR
Write Recovery Time 0
____
0
____
0
____
ns
t
DW
Data Valid to End-of-Write 15
____
30
____
40
____
ns
t
HZ
Output High-Z Time
(1,2)
____
15
____
25
____
30 ns
t
DH
Data Hold Time
(4)
0
____
0
____
0
____
ns
t
WZ
Write Enable to Output in High-Z
(1,2)
____
15
____
25
____
30 ns
t
OW
Output Active from End-of-Write
(1, 2 ,4 )
0
____
0
____
0
____
ns
t
SWRD
SEM Flag Write to Read Time
5
____
5
____
5
____
ns
t
SPS
SEM Flag Contention Window
5
____
5
____
5
____
ns
2739 tbl 14b

7006S55PF8

Mfr. #:
Manufacturer:
IDT
Description:
SRAM 16K X 8 DUAL PORT SRAM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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