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CAT28LV256G-25T

P1-P3P4-P6P7-P9P10-P12
1
Doc. No. MD-1071, Rev. E© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
■ CMOS and TTL Compatible I/O
■ Automatic Page Write Operation:
– 1 to 64 Bytes in 10ms
– Page Load Timer
■ End of Write Detection:
– Toggle Bit
–
DATADATA
DATADATA
DATA Polling
■ Hardware and Software Write Protection
■ 100,000 Program/Erase Cycles
■ 100 Year Data Retention
FEATURES
■ 3.0V to 3.6V Supply
■ Read Access Times: 200/250/300 ns
■ Low Power CMOS Dissipation:
– Active: 15 mA Max.
– Standby: 150 µA Max.
■ Simple Write Operation:
– On-Chip Address and Data Latches
– Self-Timed Write Cycle with Auto-Clear
■ Fast Write Cycle Time:
– 10ms Max.
■ Commercial, Industrial and Automotive
Temperature Ranges
DESCRIPTION
The CAT28LV256 is a fast, low power, low voltage
CMOS Parallel E
2
PROM organized as 32K x 8-bits. It
requires a simple interface for in-system programming.
On-chip address and data latches, self-timed write cycle
with auto-clear and V
CC
power up/down write protection
eliminate additional timing and protection hardware.
DATA Polling and Toggle status bits signal the start and
end of the self-timed write cycle. Additionally, the
CAT28LV256 features hardware and software write
protection.
The CAT28LV256 is manufactured using Catalyst’s
advanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC–
approved 28-pin DIP, 28-pin TSOP or 32-pin PLCC
packages.
BLOCK DIAGRAM
28LV256 F01
ADDR. BUFFER
& LATCHES
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
CONTROL
LOGIC
TIMER
ROW
DECODER
COLUMN
DECODER
HIGH VOLTAGE
GENERATOR
A
6
–A
14
CE
OE
WE
A
0
–A
5
I/O
0
–I/O
7
I/O BUFFERS
32,768 x 8
E
2
PROM
ARRAY
64 BYTE PAGE
REGISTER
V
CC
DATA POLLING
AND
TOGGLE BIT
256K-Bit CMOS PARALLEL EEPROM
CAT28LV256
CAT28LV256
2
Doc. No. MD-1071, Rev. E © 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
PLCC Package (N, G)
DIP Package (P, L)
PIN CONFIGURATION
TSOP Top View (8mm X 13.4mm) (H)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
I/O
6
I/O
5
I/O
4
GND
I/O
2
A
1
A
2
V
CC
WE
A
8
A
9
A
11
OE
A
7
A
6
A
5
A
4
A
3
A
10
I/O
7
A
12
16
15
CE
I/O
3
I/O
1
I/O
0
A
0
A
13
A
14
I/O
2
V
SS
I/O
6
I/O
5
13
14
20
19
18
17
9
10
11
12
24
23
22
21
A
1
A
0
I/O
0
I/O
1
OE
A
10
CE
I/O
7
A
5
A
4
A
3
A
2
5
6
7
8
1
2
3
4
A
14
A
12
A
7
A
6
A
9
A
11
28
27
26
25
V
CC
WE
A
13
A
8
A
6
A
5
A
4
A
3
5
6
7
8
A
2
A
1
A
0
NC
9
10
11
12
I/O
0
13
A
8
A
9
A
11
NC
29
28
27
26
OE
A
10
CE
25
24
23
22
I/O
7
21
I/O
1
I/O
2
V
SS
NC
I/O
3
I/O
4
I/O
5
14 15 16 17 18 19 20
4321323130
A
7
A
12
A
14
NC
V
CC
WE
A
13
I/O
4
I/O
3
16
15
I/O
6
TOP VIEW
PIN FUNCTIONS
Pin Name Function Pin Name Function
A
0
–A
14
Address Inputs WE Write Enable
I/O
0
–I/O
7
Data Inputs/Outputs V
CC
3.0 to 3.6 V Supply
CE Chip Enable V
SS
Ground
OE Output Enable NC No Connect
CAT28LV256
3
Doc. No. MD-1071, Rev. E© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAPACITANCE T
A
= 25°C, f = 1.0 MHz
Symbol Test Max. Units Conditions
C
I/O
(1)
Input/Output Capacitance 10 pF V
I/O
= 0V
C
IN
(1)
Input Capacitance 6 pF V
IN
= 0V
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+2.0V for periods of less than 20 ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to V
CC
+1V.
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground
(2)
........... –2.0V to +V
CC
+ 2.0V
V
CC
with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(3)
........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol Parameter Min. Max. Units Test Method
N
END
(1)
Endurance 100,000 Cycles/Byte MIL-STD-883, Test Method 1033
T
DR
(1)
Data Retention 100 Years MIL-STD-883, Test Method 1008
V
ZAP
(1)
ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
I
LTH
(1)(4)
Latch-Up 100 mA JEDEC Standard 17
MODE SELECTION
Mode CE WE OE I/O Power
Read L H L D
OUT
ACTIVE
Byte Write (WE Controlled) L H D
IN
ACTIVE
Byte Write (CE Controlled) L H D
IN
ACTIVE
Standby, and Write Inhibit H X X High-Z STANDBY
Read and Write Inhibit X H H High-Z ACTIVE
P1-P3P4-P6P7-P9P10-P12

CAT28LV256G-25T

Mfr. #:
Buy CAT28LV256G-25T
Manufacturer:
ON Semiconductor
Description:
EEPROM 256K-Bit Parallel EEPROM
Lifecycle:
New from this manufacturer.
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