OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

CAT28LV256G-25T

P1-P3P4-P6P7-P9P10-P12
CAT28LV256
4
Doc. No. MD-1071, Rev. E © 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
D.C. OPERATING CHARACTERISTICS
V
CC
= 3.0V to 3.6V, unless otherwise specified
Limits
Symbol Parameter Min. Typ. Max. Units Test Conditions
I
CC
V
CC
Current (Operating, TTL) 15 mA CE = OE = V
IL
,
f = 1/t
RC
min, All I/O’s Open
I
SBC
(2)
V
CC
Current (Standby, CMOS) 150 µA CE = V
IHC
,
All I/O’s Open
I
LI
Input Leakage Current –1 1 µAV
IN
= GND to V
CC
I
LO
Output Leakage Current –5 5 µAV
OUT
= GND to V
CC
,
CE = V
IH
V
IH
(2)
High Level Input Voltage 2 V
CC
+0.3 V
V
IL
Low Level Input Voltage –0.3 0.6 V
V
OH
High Level Output Voltage 2 V I
OH
= –100µA
V
OL
Low Level Output Voltage 0.3 V I
OL
= 1.0mA
V
WI
Write Inhibit Voltage 2 V
A.C. CHARACTERISTICS, Read Cycle
V
CC
= 3.0V to 3.6V, unless otherwise specified
28LV256-20 28LV256-25 28LV256-30
Symbol Parameter Min. Max. Min. Max. Min. Max. Units
t
RC
Read Cycle Time 200 250 300 ns
t
CE
CE Access Time 200 250 300 ns
t
AA
Address Access Time 200 250 300 ns
t
OE
OE Access Time 80 100 110 ns
t
LZ
(1)
CE Low to Active Output 0 0 0 ns
t
OLZ
(1)
OE Low to Active Output 0 0 0 ns
t
HZ
(1)(3)
CE High to High-Z Output 50 55 60 ns
t
OHZ
(1)(3)
OE High to High-Z Output 50 55 60 ns
t
OH
(1)
Output Hold from Address Change 0 0 0 ns
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) V
IHC
= V
CC
–0.3V to V
CC
+0.3V.
(3) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer.
CAT28LV256
5
Doc. No. MD-1071, Rev. E© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
A.C. CHARACTERISTICS, Write Cycle
V
CC
= 3.0V to 3.6V, unless otherwise specified
28LV256-20 28LV256-25 28LV256-30
Symbol Parameter Min. Max. Min. Max. Min. Max. Units
t
WC
Write Cycle Time 10 10 10 ms
t
AS
Address Setup Time 0 0 0 ns
t
AH
Address Hold Time 100 100 100 ns
t
CS
CE Setup Time 0 0 0 ns
t
CH
CE Hold Time 0 0 0 ns
t
CW
(3)
CE Pulse Time 150 150 150 ns
t
OES
OE Setup Time 0 0 0 ns
t
OEH
OE Hold Time 0 0 0 ns
t
WP
(3)
WE Pulse Width 150 150 150 ns
t
DS
Data Setup Time 50 50 50 ns
t
DH
Data Hold Time 0 0 0 ns
t
INIT
(1)
Write Inhibit Period After Power-up 5 10 5 10 5 10 ms
t
BLC
(1)(4)
Byte Load Cycle Time 0.15 100 0.15 100 0.15 100 µs
V
cc
1.8K
C
L
= 100 pF
C
L
INCLUDES JIG CAPACITANCE
1.3K
DEVICE
UNDER
TEST
OUTPUT
INPUT PULSE LEVELS REFERENCE POINTS
2.0 V
0.6 V
V
CC
- 0.3V
0.0 V
Figure 1. A.C. Testing Input/Output Waveform
(2)
28LV256 F04
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Input rise and fall times (10% and 90%) < 10 ns.
(3) A write pulse of less than 20ns duration will not initiate a write cycle.
(4) A timer of duration t
BLC
max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin;
however a transition from HIGH to LOW within t
BLC
max. stops the timer.
Figure 2. A.C. Testing Load Circuit (example)
28LV256 F05
CAT28LV256
6
Doc. No. MD-1071, Rev. E © 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
ADDRESS
CE
OE
WE
DATA OUT
t
AS
DATA IN
DATA VALID
HIGH-Z
t
CS
t
AH
t
CH
t
WC
t
OEH
t
BLC
t
DH
t
DS
t
OES
t
WP
ADDRESS
CE
OE
WE
t
RC
DATA OUT DATA VALIDDATA VALID
t
CE
t
OE
t
OH
t
AA
t
OHZ
t
HZ
V
IH
HIGH-Z
t
LZ
t
OLZ
DEVICE OPERATION
Read
Data stored in the CAT28LV256 is transferred to the
data bus when WE is held high, and both OE and CE are
held low. The data bus is set to a high impedance state
when either CE or OE goes high. This 2-line control
architecture can be used to eliminate bus contention in
a system environment.
Byte Write
A write cycle is executed when both CE and WE are low,
and OE is high. Write cycles can be initiated using either
WE or CE, with the address input being latched on the
falling edge of WE or CE, whichever occurs last. Data,
conversely, is latched on the rising edge of WE or CE,
whichever occurs first. Once initiated, a byte write cycle
automatically erases the addressed byte and the new
data is written within 10 ms.
Figure 3. Read Cycle
28LV256 F06
Figure 4. Byte Write Cycle [
WEWE
WEWE
WE Controlled]
28LV256 F07
P1-P3P4-P6P7-P9P10-P12

CAT28LV256G-25T

Mfr. #:
Buy CAT28LV256G-25T
Manufacturer:
ON Semiconductor
Description:
EEPROM 256K-Bit Parallel EEPROM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet