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72V71660DRG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31
10
INDUSTRIAL TEMPERATURE RANGE
IDT72V71660 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 16,384 x 16,384
Figure 1. Example for Frame Alignment Measurement
TABLE 7 — FRAME ALIGNMENT REGISTER (FAR) BITS
0123 456 78 91
0
1
1
1
2
1
3
1
4
1
5
1
6
ST-BUS
®
Frame
CLK
Offset
Value
FE
Input
0123456
7
891
0
1
1
1
2
1
3
1
4
1
5
GCI
Frame
CLK
Offset
Value
FE
Input
(FD[10:0] = 06
H
)
(FD11 = 0, sample at CLK LOW
phase)
(FD[10:0] = 09
H
)
(FD11 = 1, sample at CLK HIGH
phase)
5905
drw04
Bit Name Description
15-13 Unused Must be zero for normal operation
12 CFE (Complete When Complete Frame Evaluation = 1, the Frame Evaluation is completed and bits FD11 to FD0 bits contains a valid frame alignment offset.
Frame Evaluation) This bit is reset to zero, when Start Frame Evaluation bit in the Control Register is changed from 1 to 0.
11 FD11 The falling edge of Frame Evaluation (or rising edge for GCI mode) is sampled during the CLK-HIGH phase (FD11 = 1) or during the CLK-
(Frame Delay Bit 11) LOW phase (FD11 = 0). This bit allows the measurement resolution to ½ CLK cycle. This bit is reset to zero when the Start Frame Evaluation
bit of the Control Register changes from 1 to 0.
10-0 FD10-0 The binary value expressed in these bits refers to the measured input offset value. These bits are reset to zero when the Start Frame Evaluation
(Frame Delay Bits) bit of the Control Register changes from 1 to 0. (FD10 – MSB, FD0 – LSB)
Reset Value: 0000
H.
1514131211109876543210
0 0 0 CFE FD11 FD10 FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0
11
INDUSTRIAL TEMPERATURE RANGE
IDT72V71660 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 16,384 x 16,384
TABLE 8 — FRAME INPUT OFFSET REGISTER (FOR) BITS
NOTE:
1. n denotes an input stream number from 0 to 63.
Reset Value:0000H for all FOR registers.
Register 15 14 13 12 11 10 9876543210
FOR0 Register OF32 OF31 OF30 DLE3 OF22 OF21 OF20 DLE2 OF12 OF11 OF10 DLE1 OF02 OF01 OF00 DLE0
FOR1 Register OF72 OF71 OF70 DLE7 OF62 OF61 OF60 DLE6 OF52 OF51 OF50 DLE5 OF42 OF41 OF40 DLE4
FOR2 Register OF112 OF111 OF110 DLE11 OF102 OF101 OF100 DLE10 OF92 OF91 OF90 DLE9 OF82 OF81 OF80 DLE8
FOR3 Register OF152 OF151 OF150 DLE15 OF142 OF141 OF140 DLE14 OF132 OF131 OF130 DLE13 OF122 OF121 OF120 DLE12
FOR4 Register OF192 OF191 OF190 DLE19 OF182 OF181 OF180 DLE18 OF172 OF171 OF170 DLE17 OD162 OD161 OF160 DLE16
FOR5 Register OF232 OF231 OF230 DLE23 OF222 OF221 OF220 DLE22 OF212 OF211 OF210 DLE21 OF202 OF201 OF200 DLE20
FOR6 Register OF272 OF271 OF270 DLE27 OF262 OF261 OF260 DLE26 OF252 OF251 OF250 DLE25 OF242 OF241 OF240 DLE24
FOR7 Register OF312 OF311 OF310 DLE31 OF302 OF301 OF300 DLE30 OF292 OF291 OF290 DLE29 OF282 OF281 OF280 DLE28
FOR8 Register OF352 OF351 OF350 DLE35 OF342 OF341 OF340 DLE34 OF332 OF331 OF330 DLE33 OF322 OF321 OF320 DLE32
FOR9 Register OF392 OF391 OF390 DLE39 OF382 OF381 OF380 DLE38 OF372 OF371 OF370 DLE37 OF362 OF361 OF360 DLE36
FOR10 Register OF432 OF431 OF430 DLE43 OF422 OF421 OF420 DLE42 OF412 OF411 OF410 DLE41 OF402 OF401 OF400 DLE40
FOR11 Register OF472 OF471 OF470 DLE47 OF462 OF461 OF460 DLE46 OF452 OF451 OF450 DLE45 OF442 OF441 OF440 DLE44
FOR12 Register OF512 OF511 OF510 DLE51 OF502 OF501 OF500 DLE50 OF492 OF491 OF490 DLE49 OF482 OF481 OF480 DLE48
FOR13 Register OF552 OF551 OF550 DLE55 OF542 OF541 OF540 DLE54 OF532 OF531 OF530 DLE53 OF522 OF521 OF520 DLE52
FOR14 Register OF592 OF591 OF590 DLE59 OF582 OF581 OF580 DLE58 OF572 OF571 OF570 DLE57 OF562 OF561 OF560 DLE56
FOR15 Register OF632 OF631 OF630 DLE63 OF622 OF621 OF620 DLE62 OF612 OF611 OF610 DLE61 OF602 OF601 OF600 DLE60
Name
(1)
Description
OFn2, OFn1, OFn0 These three bits define how long the serial interface receiver takes to recognize and store bit 0 from the RX input pin: i.e., to start a new frame.
(Offset Bits 2, 1 & 0) The input frame offset can be selected to +7.5 clock periods from the point where the external frame pulse input signal is applied to the FP
input of the device. See Figure 2.
DLEn ST-BUS
®
and DLEn = 0, offset is on the clock boundary
GCI mode: DLEn = 1, offset is a half clock cycle off of the clock boundary.
12
INDUSTRIAL TEMPERATURE RANGE
IDT72V71660 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 16,384 x 16,384
Measurement Result from Corresponding
Input Stream Frame Delay Bits Offset Bits
Offset
FD11 FD2 FD1 FD0 OFn2 OFn1 OFn0 DLEn
No clock period shift (Default) 10000000
+ 0.5 clock period shift 00000001
+ 1.0 clock period shift 10010010
+ 1.5 clock period shift 00010011
+ 2.0 clock period shift 10100100
+ 2.5 clock period shift 00100101
+ 3.0 clock period shift 10110110
+ 3.5 clock period shift 00110111
+ 4.0 clock period shift 11001000
+ 4.5 clock period shift 01001001
+5.0 clock period shift 11011010
+5.5 clock period shift 01011011
+6.0 clock period shift 11101100
+6.5 clock period shift 01101101
+7.0 clock period shift 11111110
+7.5 clock period shift 01111111
TABLE 9 — OFFSET BITS (OFn2, OFn1, OFn0, DLEn) & FRAME DELAY BITS
(FD11, FD2-0)
Figure 2. Examples for Input Offset Delay Timing in 16.384Mb/s mode
FP (ST-BUS
®)
RX Stream
(16.384 Mb/s)
5905 drw05
Bit 7
Bit 7
CLK
Bit 6
offset = 0, DLE = 0
offset = 1, DLE = 0
offset = 0, DLE = 1
FP (GCI)
Bit 0
Bit 0
offset = 0, DLE = 0
offset = 1, DLE = 0
offset = 0, DLE = 1
Bit 1
Bit 0
Bit 2
Bit 1
Bit 2
Bit 1
Bit 2
RX Stream
(16.384 Mb/s)
CLK
RX Stream
(16.384 Mb/s)
RX Stream
(16.384 Mb/s)
Bit 6
Bit 5
Bit 4
Bit 5Bit 6
Bit 7
Bit 5
Bit 4
RX Stream
(16.384 Mb/s)
RX Stream
(16.384 Mb/s)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31

72V71660DRG

Mfr. #:
Buy 72V71660DRG
Manufacturer:
IDT
Description:
Digital Bus Switch ICs 3.3V Time Slot Dig Switch 16.384Mb
Lifecycle:
New from this manufacturer.
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