5
INDUSTRIAL TEMPERATURE RANGE
IDT72V71660 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 16,384 x 16,384
DESCRIPTION (CONTINUED)
The 64 serial input streams (RX) of the IDT72V71660 can run up to
16.384Mb/s allowing 256 channels per 125μs frame. The data rates on the
output streams (TX) are identical to those on the input streams (RX).
With two main operating modes, Processor Mode and Connection Mode, the
IDT72V71660 can easily switch data from incoming serial streams (Data
Memory) or from the controlling microprocessor via Connection Memory. As
control and status information is critical in data transmission, the Processor Mode
is especially useful when there are multiple devices sharing the input and output
streams.
With data coming from multiple sources and through different paths, data
entering the device is often delayed. To handle this problem, the IDT72V71660
has a Frame Evaluation feature to allow individual streams to be offset from the
frame pulse in half clock-cycle intervals up to +7.5 clock cycles.
The IDT72V71660 also provides a JTAG Test Access Port, memory block
programming, a simple microprocessor interface and automatic ST-BUS
®
/GCI
sensing to shorten setup time, aid in debugging and ease use of the device
without sacrificing capabilities.
FUNCTIONAL DESCRIPTION
DATA AND CONNECTION MEMORY
All data that comes in through the RX inputs go through a serial-to-parallel
conversion before being stored into internal Data Memory. The 8 KHz frame
pulse (FP) is used to mark the 125μs frame boundaries and to sequentially
address the input channels in Data Memory.
Data output on the TX streams may come from either the serial input streams
(Data Memory) or from the microprocessor (Connection Memory). In the case
that RX input data is to be output, the addresses in Connection Memory are used
to specify a stream and channel of the input. The Connection Memory is setup
in such a way that each location corresponds to an output channel for each
particular stream. In that way, more than one channel can output the same data.
In Processor Mode, the microprocessor writes data to the Connection Memory
locations corresponding to the stream and channel that is to be output. The lower
half (8 least significant bits) of the Connection Memory is output every frame until
the microprocessor changes the data or mode of the channel. By using this
Processor Mode capability, the microprocessor can access input and output
time-slots on a per-channel basis.
The two most significant bits of the Connection Memory are used to control
the per-channel mode of the out put streams. Specifically, the MOD1-0 bits are
used to select Processor Mode, Constant or Variable delay Mode, and the high-
impedance state of output drivers. If the MOD1-0 bits are set to 1-1 accordingly,
only that particular output channel (8 bits) will be in the high-impedance state.
If however, the ODE input pin is LOW and the Output Standby Bit in the Control
Register is LOW, all of the outputs will be in a high-impedance state even if a
particular channel in Connection Memory has enabled the output for that
channel. In other words, the ODE pin and Output Stand By control bit are master
output enables for the device (See Table 3).
SERIAL DATA INTERFACE TIMING
When a 16.384Mb/s serial data rate is required, the master clock frequency
will be running at 16.384 MHz resulting in a single-bit per clock. For all other
cases, 2.048Mb/s, 4.096Mb/s, and 8.192Mb/s, the master clock frequency will
be twice the data rate on the serial streams, resulting in two clocks per bit. Use
Table 5 to determine clock speed and the DR1-0 bits in the Control Register to
setup the device. The IDT72V71660 provides two different interface timing
modes, ST-BUS
®
or GCI. The IDT72V71660 automatically detects the pres-
ence of an input frame pulse and identifies it as either ST-BUS
®
or GCI.
In ST-BUS
®
, when running at 16.384 MHz, data is clocked out on the falling
edge and is clocked in on the subsequent rising-edge. At all other data rates,
there are two clock cycles per bit and every second falling edge of the master
clock marks a bit boundary and the data is clocked in on the rising edge of CLK,
three quarters of the way into the bit cell. See Figure 14 for timing.
In GCI format, when running at 16.384 MHz, data is clocked out on the rising
edge and is clocked in on the subsequent falling edge. At all other data rates,
there are two clock cycles per bit and every second rising edge of the master
clock marks the bit boundary and data is clocked in on the falling edge of CLK
at three quarters of the way into the bit cell. See Figure 15 for timing.
INPUT FRAME OFFSET SELECTION
Input frame offset selection allows the channel alignment of individual input
streams to be offset with respect to the output stream channel alignment . Although
all input data comes in at the same speed, delays can be caused by variable
path serial backplanes and variable path lengths which may be implemented
in large centralized and distributed switching systems. Because data is often
delayed, this feature is useful in compensating for the skew between input
streams.
Each input stream can have its own delay offset value by programming the
frame input offset registers (FOR, Table 8). The maximum allowable skew is +7.5
master clock (CLK) periods forward with a resolution of ½ clock period, see
Table 9. The output frame cannot be adjusted.
SERIAL INPUT FRAME ALIGNMENT EVALUATION
The IDT72V71660 provides the Frame Evaluation input to determine
different data input delays with respect to the frame pulse FP. A measurement
cycle is started by setting the Start Frame Evaluation bit of the Control Register
LOW for at least one frame. When the Start Frame Evaluation bit in the Control
Register is changed from LOW to HIGH, the evaluation starts. Two frames later,
the Complete Frame Evaluation bit of the Frame Alignment Register changes
from LOW to HIGH to signal that a valid offset measurement is ready to be read
from bits 0 to 11 of the Frame Alignment Register. The Start Frame Evaluation
bit must be set to zero before a new measurement cycle is started.
In ST-BUS
®
mode, the falling edge of the frame measurement signal (Frame
Evaluation) is evaluated against the falling edge of the ST-BUS
®
frame pulse.
In GCI mode, the rising edge of Frame Evaluation is evaluated against the rising
edge of the GCI frame pulse. See Table 7 and Figure 1 for the description of
the Frame Alignment Register.
MEMORY BLOCK PROGRAMMING
The IDT72V71660 provides users with the capability of initializing the entire
Connection Memory block in two frames. To set bits 14 and 15 of every
Connection Memory location, first program the desired pattern in the Block
Programming Data Bits (BPD 1-0), located in bits 7 and 8 of the Control Register.
The block programming mode is enabled by setting the Memory Block
Program bit of the Control Register HIGH. When the Block Programming Enable
bit of the Control Register is set to HIGH, the Block Programming Data will be
loaded into the bits 14 and 15 of every Connection Memory location. The other
Connection Memory bits (bit 0 to bit 13) are loaded with zeros. When the memory
block programming is complete, the device resets the Block Programming
Enable , BPD 1-0 and MBP bits to zero.
