AR0130CS
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14
FEATURES
See the AR0130 Register Reference for additional details.
Reset
The AR0130 may be reset by using RESET_BAR (active
LOW) or the reset register.
Hard Reset of Logic
The RESET_BAR pin can be connected to an external RC
circuit for simplicity. The recommended RC circuit uses a
10 kW resistor and a 0.1 mF capacitor. The rise time for the
RC circuit is 1 ms maximum.
Soft Reset of Logic
Soft reset of logic is controlled by the R0x301A Reset
register. Bit 0 is used to reset the digital logic of the sensor
while preserving the existing two−wire serial interface
configuration. Furthermore, by asserting the soft reset, the
sensor aborts the current frame it is processing and starts a
new frame. This bit is a self−resetting bit and also returns to
“0” during two−wire serial interface reads.
Clocks
The AR0130 requires one clock input (EXTCLK).
PLL−Generated Master Clock
The PLL contains a prescaler to divide the input clock
applied on EXTCLK, a VCO to multiply the prescaler
output, and two divider stages to generate the output clock.
The clocking structure is shown in Figure 12. PLL control
registers can be programmed to generate desired master
clock frequency.
NOTE: The PLL control registers must be programmed
while the sensor is in the software Standby state.
The effect of programming the PLL divisors
while the sensor is in the streaming state is
undefined.
Figure 12. PLL−Generated Master Clock PLL Setup
Pre PLL
Div
(PFD)
Pre_pll_clk_div
EXTCLK
PLL
Multiplier
(VCO)
PLL Output
Div 1
SYSCLK
PIXCLK
vt_pix_clk_divvt_sys_clk_div
PLL Input
Clock
PLL Output
Clock
PLL Output
Div 2
pll_multiplier
The PLL is enabled by default on the AR0130.
To Configure and Use the PLL:
1. Bring the AR0130 up as normal; make sure that
f
EXTCLK is between 6 and 50MHz and ensure the
sensor is in software standby (R0x301A[2]= 0).
PLL control registers must be set in software
standby.
2. Set pll_multiplier, pre_pll_clk_div,
vt_sys_clk_div, and vt_pix_clk_div based on the
desired input (f
EXTCLK
) and output (f
PIXCLK
)
frequencies. Determine the M, N, P1, and P2
values to achieve the desired f
PIXCLK
using this
formula:
f
PIXCLK
= (f
EXTCLK
× M) / (N × P1 x P2)
where
M = PLL_Multiplier (R0x3030)
N = Pre_PLL_Clk_Div (R0x302E)
P1 = Vt_Sys_Clk_Div (R0x302C)
P2 = Vt_PIX_Clk_Div (R0x302A)
3. Wait 1 ms to ensure that the VCO has locked.
4. Set R0x301A[2]=1 to enable streaming and to
switch from EXTCLK to the PLL−generated
clock.
NOTES:
1. The PLL can be bypassed at any time (sensor will
run directly off EXTCLK) by setting
R0x30B0[14]=1. However, only the parallel data
interface is supported with the PLL bypassed. The
PLL is always bypassed in software standby mode.
To disable the PLL, the sensor must be in standby
mode (R0x301A[2] = 0)
2. The following restrictions apply to the PLL tuning
parameters:
32 ≤ M ≤ 255
1 ≤ N ≤ 63
1 ≤ P1 ≤ 16
4 ≤ P2 ≤ 16
Additionally, the VCO frequency, defined as
f
VCO
= f
EXTCLK
× M / N
must be within 384 −768 MHz and the EXTCLK
