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SI1922EDH-T1-GE3

P1-P3P4-P6P7-P9P10-P12
L
c
E
E
1
e
D
e
1
A
2
A
A
1
1
-A-
b
-B-
23
654
Package Information
Vishay Siliconix
Document Number: 71154
06-Jul-01
www.vishay.com
1
SCĆ70: 6ĆLEADS
MILLIMETERS INCHES
Dim Min Nom Max Min Nom Max
A
0.90 – 1.10 0.035 – 0.043
A
1
– – 0.10 – – 0.004
A
2
0.80 – 1.00 0.031 – 0.039
b
0.15 – 0.30 0.006 – 0.012
c
0.10 – 0.25 0.004 – 0.010
D
1.80 2.00 2.20 0.071 0.079 0.087
E
1.80 2.10 2.40 0.071 0.083 0.094
E
1
1.15 1.25 1.35 0.045 0.049 0.053
e
0.65BSC 0.026BSC
e
1
1.20 1.30 1.40 0.047 0.051 0.055
L
0.10 0.20 0.30 0.004 0.008 0.012
7_Nom 7_Nom
ECN: S-03946—Rev. B, 09-Jul-01
DWG: 5550
AN816
Vishay Siliconix
Document Number: 71405
12-Dec-03
www.vishay.com
1
Dual-Channel LITTLE FOOTR 6-Pin SC-70 MOSFET
Copper Leadframe Version
Recommended Pad Pattern and Thermal Performance
INTRODUCTION
The new dual 6-pin SC-70 package with a copper leadframe
enables improved on-resistance values and enhanced
thermal performance as compared to the existing 3-pin and
6-pin packages with Alloy 42 leadframes. These devices are
intended for small to medium load applications where a
miniaturized package is required. Devices in this package
come in a range of on-resistance values, in n-channel and
p-channel versions. This technical note discusses pin-outs,
package outlines, pad patterns, evaluation board layout, and
thermal performance for the dual-channel version.
PIN-OUT
Figure 1 shows the pin-out description and Pin 1 identification
for the dual-channel SC-70 device in the 6-pin configuration.
Both n-and p-channel devices are available in this package –
the drawing example below illustrates the p-channel device.
FIGURE 1.
SOT-363
SC-70 (6-LEADS)
6
4
1
2
3
5
Top View
S
1
G
1
D
2
D
1
G
2
S
2
For package dimensions see outline drawing SC-70 (6-Leads)
(http://www.vishay.com/doc?71154)
BASIC PAD PATTERNS
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/doc?72286) for the SC-70
6-pin basic pad layout and dimensions. This pad pattern is
sufficient for the low-power applications for which this package
is intended. Increasing the drain pad pattern (Figure 2) yields
a reduction in thermal resistance and is a preferred footprint.
FIGURE 2. SC-70 (6 leads) Dual
48 (mil)
16 (mil)
654
321
61 (mil)
26 (mil)
8 (mil)
0.0 (mil)
23 (mil)
71 (mil)
96 (mil)
26 (mil)
87 (mil)
EVALUATION BOARD FOR THE DUAL-
CHANNEL SC70-6
The 6-pin SC-70 evaluation board (EVB) shown in Figure 3
measures 0.6 in. by 0.5 in. The copper pad traces are the same
as described in the previous section, Basic Pad Patterns. The
board allows for examination from the outer pins to the 6-pin
DIP connections, permitting test sockets to be used in
evaluation testing.
The thermal performance of the dual 6-pin SC-70 has been
measured on the EVB, comparing both the copper and Alloy
42 leadframes. This test was then repeated using the 1-inch
2
PCB with dual-side copper coating.
A helpful way of displaying the thermal performance of the
6-pin SC-70 dual copper leadframe is to compare it to the
traditional Alloy 42 version.
AN816
Vishay Siliconix
www.vishay.com
2
Document Number: 71405
12-Dec-03
FIGURE 3.
Front of Board SC70-6 Back of Board SC70-6
D1
G2
S2
S1
G1
D2
SC70−6 DUAL
vishay.com
THERMAL PERFORMANCE
Junction-to-Foot Thermal Resistance
(the Package Performance)
Thermal performance for the dual SC-70 6-pin package is
measured as junction-to-foot thermal resistance, in which the
“foot” is the drain lead of the device as it connects with the
body. The junction-to-foot thermal resistance for this device is
typically 80_C/W, with a maximum thermal resistance of
approximately 100_C/W. This data compares favorably with
another compact, dual-channel package – the dual TSOP-6 –
which features a typical thermal resistance of 75_C/W and a
maximum of 90_C/W.
Power Dissipation
The typical Rθ
JA
for the dual-channel 6-pin SC-70 with a
copper leadframe is 224_ C/W steady-state, compared to
413_C/W for the Alloy 42 version. All figures are based on the
1-inch
2
FR4 test board. The following example shows how the
thermal resistance impacts power dissipation for the dual 6-pin
SC-70 package at varying ambient temperatures.
Alloy 42 Leadframe
ALLOY 42 LEADFRAME
Room Ambient 25 _C Elevated Ambient 60 _C
P
D
+
T
J(max)
* T
A
Rq
JA
P
D
+
150
o
C * 25
o
C
413
o
CńW
P
D
+ 303 mW
P
D
+
T
J(max)
* T
A
Rq
JA
P
D
+
150
o
C * 60
o
C
413
o
CńW
P
D
+ 218 mW
COOPER LEADFRAME
Room Ambient 25 _C Elevated Ambient 60 _C
P
D
+
T
J(max)
* T
A
Rq
JA
P
D
+
150
o
C * 25
o
C
224
o
CńW
P
D
+ 558 mW
P
D
+
T
J(max)
* T
A
Rq
JA
P
D
+
150
o
C * 60
o
C
224
o
CńW
P
D
+ 402 mW
Although they are intended for low-power applications,
devices in the 6-pin SC-70 dual-channel configuration will
handle power dissipation in excess of 0.5 W.
TESTING
To further aid the comparison of copper and Alloy 42
leadframes, Figures 4 and 5 illustrate the dual-channel 6-pin
SC-70 thermal performance on two different board sizes and
pad patterns. The measured steady-state values of Rθ
JA
for
the dual 6-pin SC-70 with varying leadframes are as follows:
LITTLE FOOT 6-PIN SC-70
Alloy 42 Copper
1) Minimum recommended pad pattern on
the EVB board (see Figure 3).
518_C/W 344_C/W
2) Industry standard 1-inch
2
PCB with
maximum copper both sides.
413_C/W 224_C/W
The results indicate that designers can reduce thermal
resistance (θJA) by 34% simply by using the copper leadframe
device as opposed to the Alloy 42 version. In this example, a
174_C/W reduction was achieved without an increase in board
area. If an increase in board size is feasible, a further 120_C/W
reduction can be obtained by utilizing a 1-inch
2
. PCB area.
The Dual copper leadframe versions have the following suffix:
Dual: Si19xxEDH
Compl.: Si15xxEDH
P1-P3P4-P6P7-P9P10-P12

SI1922EDH-T1-GE3

Mfr. #:
Buy SI1922EDH-T1-GE3
Manufacturer:
Vishay / Siliconix
Description:
MOSFET 20V Vds 8V Vgs SC70-6
Lifecycle:
New from this manufacturer.
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