9DB102BGILF Datasheet 9DB102BGLFT, 9DB102BGILFT, 9DB102BGILF | P4-P6

IDT

Two Output Differential Buffer for PCIe Gen1 & Gen2 852 REV Q 08/27/13

ICS9DB102

Two Output Differential Buffer for PCIe Gen1 & Gen2

Electrical Characteristics - PCIEX 0.7V Current Mode Differential Pair

= Tambient; V

= 3.3 V +/-5%; C

=2pF, R

=33.2

Ω

, R

=49.9

Ω

, I

REF

= 475

Ω

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES

Current Source Output

Impedance

Zo V

= V

3000

Ω

Voltage High VHigh 660 850 1,3

Voltage Low VLow -150 150 1,3

Max Voltage Vovs 1150 1,3

Min Voltage Vuds -300 1,3

Crossing Voltage (abs) Vcross(abs) 250 350 550 mV 1,3

Crossing Voltage (var) d-Vcross

Variation of crossing over all

edges

12 140 mV 1,3

Long Accuracy ppm see Tperiod min-max values 0 ppm 1,2

100.00MHz nominal 9.9970 10.0030 ns 2

100.00MHz spread 9.9970 10.0533 ns 2

Absolute min period Tabsmin 100.00MHz nominal/spread 9.8720 ns 1,2

Rise Time t

= 0.175V, V

= 0.525V 175 700 ps 1

Fall Time t

= 0.525V V

= 0.175V 175 700 ps 1

Rise Time Variation d-t

30 125 ps 1

Fall Time Variation d-t

30 125 ps 1

PLL Mode. 0 150 ps 1

Bypass mode 3.7 4.2 ns 1

Duty Cycle d

Measurement from differential

wavefrom

45 55 % 1

Output-to-Output Skew t

sk3

= 50% 25 ps 1

jcyc-cyc

PLL mode. Measurement from

differential wavefrom

35 ps 1

jcyc-cycbyp

Additve Jitter in Bypass Mode 30 ps 1

Guaranteed by design, not 100% tested in production.

REF

= V

/(3xR

). For R

= 475

Ω

(1%), I

REF

= 2.32mA. I

= 6 x I

REF

and V

= 0.7V @ Z

=50

Ω

The 9DB102 does not add a ppm error to the input clock

Input to Output Delay

Jitter, Cycle to cycle

Measurement on single ended

signal using absolute value.

Average period Tperiod

Statistical measurement on

single ended signal using

IDT

Two Output Differential Buffer for PCIe Gen1 & Gen2 852 REV Q 08/27/13

ICS9DB102

Two Output Differential Buffer for PCIe Gen1 & Gen2

Electrical Characteristics - PLL Parameters

= Tambient; Supply Voltage V

= 3.3 V +/-5%

Grou

Parameter Descri

tion Min T

Max Units Notes

PLL Jitter Peaking j

peak-hibw

(PLL_BW = 1) 0 1 2.5 dB 1,4

PLL Jitter Peaking j

peak-lobw

(PLL_BW = 0) 0 1 2 dB 1,4

PLL Bandwidth pll

HIBW

(PLL_BW = 1) 2 2.5 3 MHz 1,5

PLL Bandwidth pll

LOBW

(PLL_BW = 0) 0.4 0.5 1 MHz 1,5

PCIe Gen 1 phase jitter

(1.5 - 22 MHz)

40 108 ps 1,2,3

PCIe Gen 2 jitter

(8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz

(PLL_BW=1)

2.7 3.1 ps rms 1,2,3

PCIe Gen 2 jitter

(8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz

(PLL_BW=0)

2.2 3.1 ps rms 1,2,3

PCIe Gen 2 jitter

(8-16 MHz, 5-16 MHz) Lo-Band <1.5MHz

1.3 3 ps rms 1,2,3

NOTES:

1. Guaranteed by design and characterization, not 100% tested in production.

2. See http://www.pcisig.com for complete specs

3. Device driven by 932S421BGLF or equivalent

Measured as maximum pass band gain. At f requencies w ithin the loop BW, highest point of magnification is called PLL jitter peaking.

Measured at 3 db dow n or half pow er point.

Jitter, Phase t

jphasePLL

IDT

Two Output Differential Buffer for PCIe Gen1 & Gen2 852 REV Q 08/27/13

ICS9DB102

Two Output Differential Buffer for PCIe Gen1 & Gen2

Common Recommendations for Differential Routing Dimension or Value Unit Figure

L1 length, route as non-coupled 50ohm trace 0.5 max inch 1

L2 length, route as non-coupled 50ohm trace 0.2 max inch 1

L3 length, route as non-coupled 50ohm trace 0.2 max inch 1

Rs 33 ohm 1

Rt 49.9 ohm 1

Down Device Differential Routing

L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max inch 1

L4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max inch 1

Differential Routing to PCI Express Connector

L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max inch 2

L4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max inch 2

SRC Reference Clock

HCSL Output Buffer

L1'

L2'

L4'

L3L3'

Rt Rt

PCI Express

Down Device

REF_CLK Input

Figure 1: Down Device Routing

HCSL Output Buffer

L1'

L2'

L4'

L3L3'

Rt Rt

PCI Express

Add-in Board

REF_CLK Input

Figure 2: PCI Express Connector Routing

P1-P3 P4-P6 P7-P9 P10-P12 P13-P13

9DB102BGILF

Mfr. #:

Buy 9DB102BGILF

Manufacturer:

IDT

Description:

Clock Buffer 2 OUTPUT PCIE GEN2 BUFFER

Lifecycle:

New from this manufacturer.

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9DB102BGILF

9DB102BGILF

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